phy: Add driver for Rockchip Naneng eDP Transmitter PHY
DPTPHYT22ULP is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit transmitter macro which enable speed up to 4.0Gbps data transmitter with optimized power and die size, also it can be easily fabricated and implemented in a video system. The AUX channel is a halfduplex, bidirectional channel consisting of one differential pair, supporting the bit rate of about 1Mbps. Macro consists of multi-main link transmitter channels, AUX channel, one PLL and bias-gen unit. The main link transmitter performs dedicated P2S, clock generator, driver with preemphasis and self-test. Each of the channels can be turned off individually. Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: Ic60d8bb86a53f686e8c46323b58d099c727a36d3
This commit is contained in:
Wyon Bi
Jianhong Chen
parent
672d3078db
commit
cf9110094e
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@ -77,6 +77,12 @@ config PHY_ROCKCHIP_INNO_USB3
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help
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Support for Rockchip USB 3.0 PHY with Innosilicon IP block.
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config PHY_ROCKCHIP_NANENG_EDP
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bool "Support Rockchip Naneng eDP Transmitter PHY"
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depends on PHY && ARCH_ROCKCHIP
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help
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Support for Rockchip eDP Transmitter PHY with Naneng IP block.
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config PHY_ROCKCHIP_TYPEC
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bool "Support Rockchip TYPEC PHY Driver"
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depends on PHY && ARCH_ROCKCHIP
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@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
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obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
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obj-$(CONFIG_PHY_ROCKCHIP_NANENG_USB2) += phy-rockchip-naneng-usb2.o
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obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o
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obj-$(CONFIG_PHY_ROCKCHIP_NANENG_EDP) += phy-rockchip-naneng-edp.o
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obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
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obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
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obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
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@ -0,0 +1,326 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#define HIWORD_UPDATE(x, h, l) ((((x) << (l)) & GENMASK((h), (l))) | \
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(GENMASK((h), (l)) << 16))
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#define EDP_PHY_GRF_CON0 0x0000
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#define EDP_PHY_TX_IDLE(x) HIWORD_UPDATE(x, 11, 8)
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#define EDP_PHY_TX_PD(x) HIWORD_UPDATE(x, 7, 4)
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#define EDP_PHY_IDDQ_EN(x) HIWORD_UPDATE(x, 1, 1)
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#define EDP_PHY_PD_PLL(x) HIWORD_UPDATE(x, 0, 0)
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#define EDP_PHY_GRF_CON1 0x0004
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#define EDP_PHY_PLL_DIV(x) HIWORD_UPDATE(x, 14, 0)
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#define EDP_PHY_GRF_CON2 0x0008
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#define EDP_PHY_TX_RTERM(x) HIWORD_UPDATE(x, 10, 8)
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#define EDP_PHY_RATE(x) HIWORD_UPDATE(x, 5, 4)
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#define EDP_PHY_REF_DIV(x) HIWORD_UPDATE(x, 3, 0)
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#define EDP_PHY_GRF_CON3 0x000c
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#define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, \
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4 * (lane))
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#define EDP_PHY_GRF_CON4 0x0010
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#define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, \
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4 * (lane))
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#define EDP_PHY_GRF_CON5 0x0014
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#define EDP_PHY_TX_MODE(x) HIWORD_UPDATE(x, 9, 8)
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#define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, \
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2 * (lane))
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#define EDP_PHY_GRF_CON6 0x0018
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#define EDP_PHY_SSC_DEPTH(x) HIWORD_UPDATE(x, 15, 12)
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#define EDP_PHY_SSC_EN(x) HIWORD_UPDATE(x, 11, 11)
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#define EDP_PHY_SSC_CNT(x) HIWORD_UPDATE(x, 9, 0)
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#define EDP_PHY_GRF_CON7 0x001c
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#define EDP_PHY_GRF_CON8 0x0020
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#define EDP_PHY_PLL_CTL_H(x) HIWORD_UPDATE(x, 15, 0)
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#define EDP_PHY_GRF_CON9 0x0024
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#define EDP_PHY_TX_CTL(x) HIWORD_UPDATE(x, 15, 0)
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#define EDP_PHY_GRF_CON10 0x0028
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#define EDP_PHY_AUX_RCV_PD_SEL(x) HIWORD_UPDATE(x, 5, 5)
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#define EDP_PHY_AUX_DRV_PD_SEL(x) HIWORD_UPDATE(x, 4, 4)
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#define EDP_PHY_AUX_IDLE(x) HIWORD_UPDATE(x, 2, 2)
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#define EDP_PHY_AUX_RCV_PD(x) HIWORD_UPDATE(x, 1, 1)
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#define EDP_PHY_AUX_DRV_PD(x) HIWORD_UPDATE(x, 0, 0)
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#define EDP_PHY_GRF_CON11 0x002c
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#define EDP_PHY_AUX_RCV_VCM(x) HIWORD_UPDATE(x, 14, 12)
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#define EDP_PHY_AUX_MODE(x) HIWORD_UPDATE(x, 11, 10)
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#define EDP_PHY_AUX_AMP_SCALE(x) HIWORD_UPDATE(x, 9, 8)
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#define EDP_PHY_AUX_AMP(x) HIWORD_UPDATE(x, 6, 4)
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#define EDP_PHY_AUX_RTERM(x) HIWORD_UPDATE(x, 2, 0)
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#define EDP_PHY_GRF_STATUS0 0x0030
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#define PLL_RDY BIT(0)
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#define EDP_PHY_GRF_STATUS1 0x0034
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struct rockchip_edp_phy {
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void __iomem *regs;
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struct udevice *dev;
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struct reset_ctl apb_reset;
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};
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static struct {
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int amp;
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int amp_scale;
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int emp;
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} vp[4][4] = {
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{ {0x1, 0x1, 0x0}, {0x2, 0x1, 0x4}, {0x3, 0x1, 0x8}, {0x4, 0x1, 0xd} },
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{ {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
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{ {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
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{ {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
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};
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static int rockchip_edp_phy_set_voltages(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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u8 lane;
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u32 val;
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for (lane = 0; lane < dp->lanes; lane++) {
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val = vp[dp->voltage[lane]][dp->pre[lane]].amp;
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writel(EDP_PHY_TX_AMP(lane, val),
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edpphy->regs + EDP_PHY_GRF_CON4);
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val = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale;
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writel(EDP_PHY_TX_AMP_SCALE(lane, val),
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edpphy->regs + EDP_PHY_GRF_CON5);
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val = vp[dp->voltage[lane]][dp->pre[lane]].emp;
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writel(EDP_PHY_TX_EMP(lane, val),
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edpphy->regs + EDP_PHY_GRF_CON3);
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}
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return 0;
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}
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static int rockchip_edp_phy_set_rate(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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u32 value;
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int ret;
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writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf),
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edpphy->regs + EDP_PHY_GRF_CON0);
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udelay(100);
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writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5);
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writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0);
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switch (dp->link_rate) {
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case 1620:
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writel(EDP_PHY_PLL_DIV(0x4380),
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edpphy->regs + EDP_PHY_GRF_CON1);
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writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x1) |
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EDP_PHY_REF_DIV(0x0), edpphy->regs + EDP_PHY_GRF_CON2);
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writel(EDP_PHY_PLL_CTL_H(0x0800),
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edpphy->regs + EDP_PHY_GRF_CON8);
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writel(EDP_PHY_TX_CTL(0x0000), edpphy->regs + EDP_PHY_GRF_CON9);
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break;
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case 2700:
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writel(EDP_PHY_PLL_DIV(0x3840),
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edpphy->regs + EDP_PHY_GRF_CON1);
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writel(EDP_PHY_TX_RTERM(0x1) | EDP_PHY_RATE(0x0) |
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EDP_PHY_REF_DIV(0x0), edpphy->regs + EDP_PHY_GRF_CON2);
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writel(EDP_PHY_PLL_CTL_H(0x0800),
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edpphy->regs + EDP_PHY_GRF_CON8);
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writel(EDP_PHY_TX_CTL(0x0000), edpphy->regs + EDP_PHY_GRF_CON9);
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break;
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}
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if (dp->ssc)
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writel(EDP_PHY_SSC_DEPTH(0x9) | EDP_PHY_SSC_EN(0x1) |
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EDP_PHY_SSC_CNT(0x17d),
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edpphy->regs + EDP_PHY_GRF_CON6);
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else
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writel(EDP_PHY_SSC_EN(0x0), edpphy->regs + EDP_PHY_GRF_CON6);
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writel(EDP_PHY_PD_PLL(0x0), edpphy->regs + EDP_PHY_GRF_CON0);
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writel(EDP_PHY_TX_PD(~GENMASK(dp->lanes - 1, 0)),
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edpphy->regs + EDP_PHY_GRF_CON0);
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ret = readl_poll_timeout(edpphy->regs + EDP_PHY_GRF_STATUS0,
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value, value & PLL_RDY, 1000);
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if (ret) {
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dev_err(edpphy->dev, "pll is not ready: %d\n", ret);
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return ret;
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}
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writel(EDP_PHY_TX_MODE(0x0), edpphy->regs + EDP_PHY_GRF_CON5);
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writel(EDP_PHY_TX_IDLE(~GENMASK(dp->lanes - 1, 0)),
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edpphy->regs + EDP_PHY_GRF_CON0);
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return 0;
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}
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static int rockchip_edp_phy_verify_config(struct rockchip_edp_phy *edpphy,
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struct phy_configure_opts_dp *dp)
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{
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int i;
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/* If changing link rate was required, verify it's supported. */
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if (dp->set_rate) {
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switch (dp->link_rate) {
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case 1620:
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case 2700:
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/* valid bit rate */
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break;
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default:
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return -EINVAL;
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}
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}
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/* Verify lane count. */
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switch (dp->lanes) {
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case 1:
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case 2:
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case 4:
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/* valid lane count. */
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break;
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default:
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return -EINVAL;
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}
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/*
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* If changing voltages is required, check swing and pre-emphasis
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* levels, per-lane.
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*/
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if (dp->set_voltages) {
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/* Lane count verified previously. */
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for (i = 0; i < dp->lanes; i++) {
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if (dp->voltage[i] > 3 || dp->pre[i] > 3)
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return -EINVAL;
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/*
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* Sum of voltage swing and pre-emphasis levels cannot
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* exceed 3.
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*/
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if (dp->voltage[i] + dp->pre[i] > 3)
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return -EINVAL;
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}
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}
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return 0;
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}
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static int rockchip_edp_phy_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev);
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int ret;
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ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev, "invalid params for phy configure\n");
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return ret;
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}
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if (opts->dp.set_rate) {
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ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev,
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"rockchip_edp_phy_set_rate failed\n");
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return ret;
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}
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}
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if (opts->dp.set_voltages) {
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ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp);
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if (ret) {
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dev_err(edpphy->dev,
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"rockchip_edp_phy_set_voltages failed\n");
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return ret;
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}
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}
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return 0;
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}
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static int rockchip_edp_phy_power_on(struct phy *phy)
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{
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struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev);
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reset_assert(&edpphy->apb_reset);
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udelay(1);
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reset_deassert(&edpphy->apb_reset);
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udelay(1);
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writel(EDP_PHY_AUX_RCV_PD(0x1) | EDP_PHY_AUX_DRV_PD(0x1) |
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EDP_PHY_AUX_IDLE(0x1), edpphy->regs + EDP_PHY_GRF_CON10);
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writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf) | EDP_PHY_PD_PLL(0x1),
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edpphy->regs + EDP_PHY_GRF_CON0);
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udelay(100);
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writel(EDP_PHY_AUX_RCV_VCM(0x4) | EDP_PHY_AUX_MODE(0x1) |
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EDP_PHY_AUX_AMP_SCALE(0x1) | EDP_PHY_AUX_AMP(0x3) |
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EDP_PHY_AUX_RTERM(0x1), edpphy->regs + EDP_PHY_GRF_CON11);
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writel(EDP_PHY_AUX_RCV_PD(0x0) | EDP_PHY_AUX_DRV_PD(0x0),
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edpphy->regs + EDP_PHY_GRF_CON10);
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udelay(100);
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writel(EDP_PHY_AUX_IDLE(0x0), edpphy->regs + EDP_PHY_GRF_CON10);
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mdelay(20);
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return 0;
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}
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static int rockchip_edp_phy_power_off(struct phy *phy)
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{
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struct rockchip_edp_phy *edpphy = dev_get_priv(phy->dev);
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writel(EDP_PHY_TX_IDLE(0xf) | EDP_PHY_TX_PD(0xf),
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edpphy->regs + EDP_PHY_GRF_CON0);
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udelay(100);
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writel(EDP_PHY_TX_MODE(0x3), edpphy->regs + EDP_PHY_GRF_CON5);
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writel(EDP_PHY_PD_PLL(0x1), edpphy->regs + EDP_PHY_GRF_CON0);
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writel(EDP_PHY_AUX_RCV_PD(0x1) | EDP_PHY_AUX_DRV_PD(0x1) |
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EDP_PHY_AUX_IDLE(0x1), edpphy->regs + EDP_PHY_GRF_CON10);
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return 0;
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}
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static struct phy_ops rockchip_edp_phy_ops = {
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.power_on = rockchip_edp_phy_power_on,
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.power_off = rockchip_edp_phy_power_off,
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.configure = rockchip_edp_phy_configure,
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};
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static int rockchip_edp_phy_probe(struct udevice *dev)
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{
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struct rockchip_edp_phy *edpphy = dev_get_priv(dev);
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int ret;
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edpphy->regs = dev_read_addr_ptr(dev);
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if (!edpphy->regs)
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return -ENOENT;
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edpphy->dev = dev;
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ret = reset_get_by_name(dev, "apb", &edpphy->apb_reset);
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if (ret < 0) {
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dev_err(dev, "failed to get apb reset: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct udevice_id rockchip_edp_phy_ids[] = {
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{ .compatible = "rockchip,rk3568-edp-phy", },
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{}
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};
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U_BOOT_DRIVER(rockchip_edp_phy) = {
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.name = "rockchip_edp_phy",
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.id = UCLASS_PHY,
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.ops = &rockchip_edp_phy_ops,
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.of_match = rockchip_edp_phy_ids,
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.probe = rockchip_edp_phy_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_edp_phy),
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};
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