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clk: rockchip: rk1808: support pclk_pmu freq setting 

set pclk_pmu freq before ppll freq setting.

Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-10-06 20:23:19 +08:00 committed by Jianhong Chen
parent b31aa7beb9
commit dad1489559
2 changed files with 26 additions and 1 deletions
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5
arch/arm/include/asm/arch-rockchip/cru_rk1808.h
View File

@ -12,6 +12,7 @@
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (600 * MHz)
#define PCLK_PMU_HZ (100 * MHz)
/* PX30 pll id */
enum rk1808_pll_id {
@ -266,5 +267,9 @@ enum {
CLK_I2C0_DIV_CON_SHIFT = 8,
CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT,
CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT,
/* PMUCRU_CLK_SEL0_CON */
PCLK_PMU_DIV_CON_SHIFT = 0,
PCLK_PMU_DIV_CON_MASK = 0x1f << PCLK_PMU_DIV_CON_SHIFT,
};
#endif

22
drivers/clk/rockchip/clk_rk1808.c
View File

@ -689,6 +689,22 @@ static ulong rk1808_peri_set_clk(struct rk1808_clk_priv *priv,
return rk1808_peri_get_clk(priv, clk_id);
}
static ulong rk1808_pclk_pmu_set_clk(struct rk1808_clk_priv *priv,
ulong clk_id, ulong parent_hz, ulong hz)
{
struct rk1808_cru *cru = priv->cru;
int src_clk_div;
src_clk_div = DIV_ROUND_UP(parent_hz, hz);
assert(src_clk_div - 1 < 31);
rk_clrsetreg(&cru->pmu_clksel_con[0],
PCLK_PMU_DIV_CON_MASK,
(src_clk_div - 1) << PCLK_PMU_DIV_CON_SHIFT);
return parent_hz / src_clk_div;
}
static ulong rk1808_armclk_set_clk(struct rk1808_clk_priv *priv, ulong hz)
{
struct rk1808_cru *cru = priv->cru;
@ -821,10 +837,14 @@ static ulong rk1808_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case PLL_APLL:
case PLL_DPLL:
case PLL_PPLL:
ret = rockchip_pll_set_rate(&rk1808_pll_clks[clk->id - 1],
priv->cru, clk->id - 1, rate);
break;
case PLL_PPLL:
ret = rk1808_pclk_pmu_set_clk(priv, clk->id, rate, PCLK_PMU_HZ);
ret = rockchip_pll_set_rate(&rk1808_pll_clks[PPLL],
priv->cru, PPLL, rate);
break;
case PLL_CPLL:
ret = rockchip_pll_set_rate(&rk1808_pll_clks[CPLL],
priv->cru, CPLL, rate);