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rockchip: rk3128: add support for video phy 

Sync the video phy related dts node from kernel.

Change-Id: I93ac2d1540934f2674702255f3f1c7913cc997d2
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi 2019-01-11 15:30:58 +08:00 committed by Jianhong Chen
parent 2ba7147f80
commit e2ce9fefd4
1 changed files with 106 additions and 32 deletions
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138
arch/arm/dts/rk3128.dtsi
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@ -375,15 +375,20 @@
#address-cells = <1>;
#size-cells = <0>;
vop_out_lvds: endpoint@1 {
reg = <1>;
vop_out_lvds: endpoint@0 {
reg = <0>;
remote-endpoint = <&lvds_in_vop>;
};
vop_out_dsi: endpoint@2 {
vop_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_vop>;
};
vop_out_rgb: endpoint@2 {
reg = <2>;
remote-endpoint = <&rgb_in_vop>;
};
};
};
@ -391,11 +396,11 @@
compatible = "rockchip,rk3128-mipi-dsi";
reg = <0x10110000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&mipi_dphy>;
clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
clock-names = "pclk", "h2p", "hs_clk";
resets = <&cru SRST_VIO_MIPI_DSI>;
reset-names = "apb";
phys = <&mipi_dphy>;
phys = <&video_phy>;
phy-names = "mipi_dphy";
rockchip,grf = <&grf>;
#address-cells = <1>;
@ -540,39 +545,19 @@
status = "disabled";
};
mipi_dphy: mipi-dphy@20038000 {
compatible = "rockchip,rk3128-mipi-dphy";
reg = <0x20038000 0x4000>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>;
clock-names = "ref", "pclk", "h2p";
clock-output-names = "mipi_dphy_pll";
video_phy: video-phy@20038000 {
compatible = "rockchip,rk3128-video-phy";
reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
<&cru PCLK_MIPI>;
clock-names = "ref", "pclk_phy", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_MIPIPHY_P>;
reset-names = "apb";
reset-names = "rst";
#phy-cells = <0>;
status = "disabled";
};
lvds: lvds@20038000 {
compatible = "rockchip,rk3126-lvds";
reg = <0x20038000 0x4000>, <0x10110000 0x100>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds_in: port@0 {
reg = <0>;
lvds_in_vop: endpoint {
remote-endpoint = <&vop_out_lvds>;
};
};
};
};
i2c0: i2c0@20072000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x20072000 0x1000>;
@ -638,6 +623,49 @@
grf: syscon@20008000 {
compatible = "rockchip,rk3128-grf", "syscon";
reg = <0x20008000 0x1000>;
lvds: lvds {
compatible = "rockchip,rk3126-lvds";
phys = <&video_phy>;
phy-names = "phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_vop: endpoint {
remote-endpoint = <&vop_out_lvds>;
};
};
};
};
rgb: rgb {
compatible = "rockchip,rk3128-rgb";
phys = <&video_phy>;
phy-names = "phy";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcdc_rgb_pins>;
pinctrl-1 = <&lcdc_sleep_pins>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
rgb_in_vop: endpoint {
remote-endpoint = <&vop_out_rgb>;
};
};
};
};
};
pinctrl: pinctrl@20008000 {
@ -772,6 +800,52 @@
};
};
lcdc {
lcdc_rgb_pins: lcdc-rgb-pins {
rockchip,pins =
<2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */
<2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */
<2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */
<2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */
<2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */
<2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */
<2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */
<2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */
<2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */
<2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */
<2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */
<2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */
<2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */
<2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */
<2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */
<2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */
<2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */
<2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */
};
lcdc_sleep_pins: lcdc-sleep-pins {
rockchip,pins =
<2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */
<2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */
<2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */
<2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */
<2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */
<2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */
<2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */
<2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */
<2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */
<2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */
<2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */
<2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */
<2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */
<2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */
<2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */
<2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */
<2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */
<2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,