phy: rockchip-inno-usb2: add usb2 phy support for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Change-Id: Ia33d3de222a6c7f263290f4098d0a5e557a9d568
This commit is contained in:
Ren Jianing
Jianhong Chen
parent
3aaa96e8af
commit
e475bd5dfd
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@ -8,8 +8,10 @@
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#include <dm.h>
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#include <dm/lists.h>
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#include <generic-phy.h>
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#include <syscon.h>
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#include <linux/ioport.h>
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#include <power/regulator.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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@ -150,18 +152,18 @@ struct rockchip_usb2phy_cfg {
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struct rockchip_usb2phy {
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u8 dcd_retries;
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u8 primary_retries;
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void __iomem *grf_base;
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void __iomem *usbgrf_base;
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struct regmap *grf_base;
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struct regmap *usbgrf_base;
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struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
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const struct rockchip_usb2phy_cfg *phy_cfg;
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};
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static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy)
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static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
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{
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return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base;
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}
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static inline int property_enable(void __iomem *base,
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static inline int property_enable(struct regmap *base,
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const struct usb2phy_reg *reg, bool en)
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{
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u32 val, mask, tmp;
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@ -170,16 +172,16 @@ static inline int property_enable(void __iomem *base,
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT);
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return writel(val, base + reg->offset);
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return regmap_write(base, reg->offset, val);
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}
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static inline bool property_enabled(void __iomem *base,
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static inline bool property_enabled(struct regmap *base,
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const struct usb2phy_reg *reg)
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{
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u32 tmp, orig;
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u32 mask = GENMASK(reg->bitend, reg->bitstart);
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orig = readl(base + reg->offset);
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regmap_read(base, reg->offset, &orig);
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tmp = (orig & mask) >> reg->bitstart;
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@ -205,7 +207,7 @@ static const char *chg_to_string(enum power_supply_type chg_type)
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static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
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bool en)
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{
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
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property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
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@ -214,7 +216,7 @@ static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
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static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
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bool en)
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{
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
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property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
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@ -223,7 +225,7 @@ static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
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static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
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bool en)
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{
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
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property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
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@ -232,13 +234,13 @@ static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
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static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy)
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{
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bool vout = false;
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struct regmap *base = get_reg_base(rphy);
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while (rphy->primary_retries--) {
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/* voltage source on DP, probe on DM */
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rockchip_chg_enable_primary_det(rphy, true);
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mdelay(CHG_PRIMARY_DET_TIME);
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vout = property_enabled(rphy->grf_base,
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&rphy->phy_cfg->chg_det.cp_det);
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vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
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if (vout)
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break;
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}
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@ -253,7 +255,7 @@ int rockchip_chg_get_type(void)
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enum power_supply_type chg_type;
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struct rockchip_usb2phy *rphy;
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struct udevice *udev;
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void __iomem *base;
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struct regmap *base;
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bool is_dcd, vout;
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int ret;
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@ -287,8 +289,7 @@ int rockchip_chg_get_type(void)
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mdelay(CHG_DCD_POLL_TIME);
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/* get data contact detection status */
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is_dcd = property_enabled(rphy->grf_base,
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&rphy->phy_cfg->chg_det.dp_det);
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is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det);
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if (is_dcd || !rphy->dcd_retries) {
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/*
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@ -302,8 +303,7 @@ int rockchip_chg_get_type(void)
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}
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mdelay(CHG_PRIMARY_DET_TIME);
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vout = property_enabled(rphy->grf_base,
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&rphy->phy_cfg->chg_det.cp_det);
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vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
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rockchip_chg_enable_primary_det(rphy, false);
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if (vout) {
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/* stage 3, voltage source on DM, probe on DP */
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@ -331,8 +331,7 @@ int rockchip_chg_get_type(void)
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}
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mdelay(CHG_SECONDARY_DET_TIME);
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vout = property_enabled(rphy->grf_base,
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&rphy->phy_cfg->chg_det.dcp_det);
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vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det);
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/* stage 4, turn off voltage source */
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rockchip_chg_enable_secondary_det(rphy, false);
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if (vout)
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@ -365,7 +364,7 @@ void otg_phy_init(struct dwc2_udc *dev)
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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struct rockchip_usb2phy *rphy;
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struct udevice *udev;
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void __iomem *base;
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struct regmap *base;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
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@ -393,7 +392,7 @@ static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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struct udevice *vbus = NULL;
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bool iddig = true;
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@ -416,7 +415,7 @@ static int rockchip_usb2phy_init(struct phy *phy)
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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if (phy->id == USB2PHY_PORT_OTG) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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@ -440,7 +439,7 @@ static int rockchip_usb2phy_exit(struct phy *phy)
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struct udevice *parent = phy->dev->parent;
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struct rockchip_usb2phy *rphy = dev_get_priv(parent);
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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if (phy->id == USB2PHY_PORT_OTG) {
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port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
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@ -546,31 +545,55 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
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const struct rockchip_usb2phy_cfg *phy_cfgs;
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struct rockchip_usb2phy *rphy = dev_get_priv(dev);
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struct udevice *parent = dev->parent;
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struct udevice *syscon;
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struct resource res;
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u32 reg, index;
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int ret;
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if (!strncmp(parent->name, "root_driver", 11) &&
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dev_read_bool(dev, "rockchip,grf"))
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rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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else
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rphy->grf_base = (void __iomem *)dev_read_addr(parent);
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dev_read_bool(dev, "rockchip,grf")) {
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"rockchip,grf", &syscon);
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if (ret) {
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dev_err(dev, "get syscon grf failed\n");
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return ret;
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}
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rphy->grf_base = syscon_get_regmap(syscon);
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} else {
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rphy->grf_base = syscon_get_regmap(parent);
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}
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if (rphy->grf_base <= 0) {
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dev_err(dev, "get syscon grf failed\n");
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dev_err(dev, "get syscon grf regmap failed\n");
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return -EINVAL;
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}
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if (dev_read_bool(dev, "rockchip,usbgrf")) {
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rphy->usbgrf_base =
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syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF);
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if (rphy->usbgrf_base <= 0) {
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"rockchip,usbgrf", &syscon);
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if (ret) {
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dev_err(dev, "get syscon usbgrf failed\n");
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return ret;
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}
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rphy->usbgrf_base = syscon_get_regmap(syscon);
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if (rphy->usbgrf_base <= 0) {
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dev_err(dev, "get syscon usbgrf regmap failed\n");
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return -EINVAL;
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}
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} else {
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rphy->usbgrf_base = NULL;
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}
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if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) {
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if (!strncmp(parent->name, "root_driver", 11)) {
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ret = dev_read_resource(dev, 0, &res);
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reg = res.start;
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} else {
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ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®);
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}
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if (ret) {
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dev_err(dev, "could not read reg\n");
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return -EINVAL;
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}
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@ -605,12 +628,12 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
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static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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{
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void __iomem *base = get_reg_base(rphy);
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struct regmap *base = get_reg_base(rphy);
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int ret = 0;
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/* Open pre-emphasize in non-chirp state for PHY0 otg port */
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if (rphy->phy_cfg->reg == 0x760)
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ret = writel(0x00070004, base + 0x76c);
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ret = regmap_write(base, 0x76c, 0x00070004);
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return ret;
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}
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@ -1028,6 +1051,80 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
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{ /* sentinel */ }
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};
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static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
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{
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.reg = 0xfe8a0000,
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.num_ports = 2,
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.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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.phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
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.bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
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.bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
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.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
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.iddig_output = { 0x0000, 10, 10, 0, 1 },
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.iddig_en = { 0x0000, 9, 9, 0, 1 },
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.idfall_det_en = { 0x0080, 5, 5, 0, 1 },
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.idfall_det_st = { 0x0084, 5, 5, 0, 1 },
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.idfall_det_clr = { 0x008c, 5, 5, 0, 1 },
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.idrise_det_en = { 0x0080, 4, 4, 0, 1 },
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.idrise_det_st = { 0x0084, 4, 4, 0, 1 },
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.idrise_det_clr = { 0x008c, 4, 4, 0, 1 },
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.ls_det_en = { 0x0080, 0, 0, 0, 1 },
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.ls_det_st = { 0x0084, 0, 0, 0, 1 },
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.ls_det_clr = { 0x008c, 0, 0, 0, 1 },
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.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
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.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
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.utmi_iddig = { 0x00c0, 6, 6, 0, 1 },
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.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x0004, 8, 0, 0, 0x1d1 },
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.ls_det_en = { 0x0080, 1, 1, 0, 1 },
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.ls_det_st = { 0x0084, 1, 1, 0, 1 },
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.ls_det_clr = { 0x008c, 1, 1, 0, 1 },
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.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
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}
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},
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.chg_det = {
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.opmode = { 0x0000, 3, 0, 5, 1 },
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.cp_det = { 0x00c0, 24, 24, 0, 1 },
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.dcp_det = { 0x00c0, 23, 23, 0, 1 },
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.dp_det = { 0x00c0, 25, 25, 0, 1 },
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.idm_sink_en = { 0x0008, 8, 8, 0, 1 },
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.idp_sink_en = { 0x0008, 7, 7, 0, 1 },
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.idp_src_en = { 0x0008, 9, 9, 0, 1 },
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.rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
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.vdm_src_en = { 0x0008, 12, 12, 0, 1 },
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.vdp_src_en = { 0x0008, 11, 11, 0, 1 },
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},
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},
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{
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.reg = 0xfe8b0000,
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.num_ports = 2,
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.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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.phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
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.ls_det_en = { 0x0080, 0, 0, 0, 1 },
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.ls_det_st = { 0x0084, 0, 0, 0, 1 },
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.ls_det_clr = { 0x008c, 0, 0, 0, 1 },
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.utmi_ls = { 0x00c0, 5, 4, 0, 1 },
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.utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x0004, 8, 0, 0, 0x1d1 },
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.ls_det_en = { 0x0080, 1, 1, 0, 1 },
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.ls_det_st = { 0x0084, 1, 1, 0, 1 },
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.ls_det_clr = { 0x008c, 1, 1, 0, 1 },
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.utmi_ls = { 0x00c0, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
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}
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},
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},
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{ /* sentinel */ }
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};
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static const struct udevice_id rockchip_usb2phy_ids[] = {
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{ .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
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{ .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
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@ -1036,6 +1133,7 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
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{ .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
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{ .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
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{ .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
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{ .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
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{ .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
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{ }
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};
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