driver: ram: rv1108: use common code to setup ddr parameter
use rockchip_setup_ddr_param to setup ddr parameter. The dram_init() and dram_init_banksize() make use of sdram common code. Change-Id: Icfc6cbef9fcc128e3a835184b46b89b9b22aab16 Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
parent
4cd861d04b
commit
e5f393836b
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@ -57,24 +57,3 @@ void board_debug_uart_init(void)
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#endif
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#endif /*CONFIG_SPL_BUILD*/
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}
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int dram_init(void)
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{
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struct rv1108_grf *grf = (void *)GRF_BASE;
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gd->ram_size = rockchip_sdram_size((phys_addr_t)&grf->os_reg2);
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return 0;
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}
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int dram_init_banksize(void)
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{
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size_t max_size = min((unsigned long)(gd->ram_size +
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CONFIG_SYS_SDRAM_BASE), gd->ram_top);
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
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return 0;
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}
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@ -2,6 +2,8 @@ CONFIG_ARM=y
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# CONFIG_SPL_USE_ARCH_MEMCPY is not set
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# CONFIG_SPL_USE_ARCH_MEMSET is not set
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ROCKCHIP_RV1108=y
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CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
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@ -16,6 +18,7 @@ CONFIG_DEBUG_UART=y
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_ANDROID_BOOTLOADER=y
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CONFIG_SPL_STACK_R=y
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CONFIG_PANIC_HANG=y
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CONFIG_TPL_TINY_FRAMEWORK=y
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CONFIG_TPL_SERIAL_SUPPORT=y
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CONFIG_FASTBOOT_BUF_ADDR=0x62000000
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@ -35,11 +38,12 @@ CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_TPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_SPL_OF_PLATDATA=y
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CONFIG_TPL_OF_PLATDATA=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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CONFIG_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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@ -16,6 +16,7 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
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obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
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obj-$(CONFIG_ROCKCHIP_PX30) += rockchip_sdram.o
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obj-$(CONFIG_ROCKCHIP_RK1808) = rockchip_sdram.o
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obj-$(CONFIG_ROCKCHIP_RV1108) += rockchip_sdram.o
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obj-$(CONFIG_ROCKCHIP_RK3036) = rockchip_sdram.o
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obj-$(CONFIG_ROCKCHIP_RK3308) = rockchip_sdram.o
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ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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@ -9,6 +9,7 @@
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_px30.h>
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#include <asm/arch/grf_rv1108.h>
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#include <asm/arch/grf_rk1808.h>
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#include <asm/arch/grf_rk3036.h>
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#include <asm/arch/grf_rk3308.h>
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@ -28,7 +29,13 @@ static int dmc_probe(struct udevice *dev)
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struct dram_info *priv = dev_get_priv(dev);
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if (!(gd->flags & GD_FLG_RELOC)) {
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#if defined(CONFIG_ROCKCHIP_RK3036)
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#if defined(CONFIG_ROCKCHIP_RV1108)
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struct rv1108_grf *grf =
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syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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priv->info.size =
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rockchip_sdram_size((phys_addr_t)&grf->os_reg2);
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#elif defined(CONFIG_ROCKCHIP_RK3036)
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struct rk3036_grf *grf =
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syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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@ -81,7 +88,9 @@ static struct ram_ops dmc_ops = {
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};
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static const struct udevice_id dmc_ids[] = {
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#if defined(CONFIG_ROCKCHIP_RK3036)
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#if defined(CONFIG_ROCKCHIP_RV1108)
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{ .compatible = "rockchip,rv1108-dmc" },
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#elif defined(CONFIG_ROCKCHIP_RK3036)
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{ .compatible = "rockchip,rk3036-dmc" },
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#elif defined(CONFIG_ROCKCHIP_RK3308)
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{ .compatible = "rockchip,rk3308-dmc" },
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@ -112,9 +112,21 @@ void *get_base_addr(unsigned int *reg, unsigned int offset)
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return (void *)p;
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}
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void get_ddr_param(struct dram_info *sdram_priv,
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struct ddr_param *ddr_param)
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{
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size_t ram_size =
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rockchip_sdram_size((phys_addr_t)&sdram_priv->grf->os_reg2);
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ddr_param->count = 1;
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ddr_param->para[0] = CONFIG_SYS_SDRAM_BASE;
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ddr_param->para[1] = ram_size;
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}
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int sdram_init(void)
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{
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int ret;
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struct ddr_param ddr_param;
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struct dram_info *sdram_priv = &info;
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struct driver_info *info =
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ll_entry_start(struct driver_info, driver_info);
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@ -136,5 +148,8 @@ int sdram_init(void)
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if (ret)
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debug("rv1108_sdram_init() fail!");
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get_ddr_param(sdram_priv, &ddr_param);
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rockchip_setup_ddr_param(&ddr_param);
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return ret;
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}
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@ -22,7 +22,7 @@
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/* SPL support */
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#define CONFIG_SPL_STACK 0x10080700
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#define CONFIG_SPL_TEXT_BASE 0x10080800
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#define CONFIG_SPL_MAX_SIZE 0x1700
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#define CONFIG_SPL_MAX_SIZE 0x4000
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/* BSS setup */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x100
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