qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: rockchip: rk1808: print arm enter and init rate 

Change-Id: I14f0b0c95b1367266fe9c64050a602ad58208d53
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-01-22 15:18:46 +08:00
parent 231617c5ab
commit ed6f5d94b5
2 changed files with 27 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/include/asm/arch-rockchip/cru_rk1808.h
View File

@ -38,6 +38,10 @@ struct rk1808_clk_priv {
ulong cpll_hz; ulong cpll_hz;
ulong gpll_hz; ulong gpll_hz;
ulong npll_hz; ulong npll_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
}; };
struct rk1808_pll { struct rk1808_pll {

28
drivers/clk/rockchip/clk_rk1808.c
View File

@ -1072,11 +1072,19 @@ static int rk1808_clk_probe(struct udevice *dev)
struct rk1808_clk_priv *priv = dev_get_priv(dev); struct rk1808_clk_priv *priv = dev_get_priv(dev);
int ret; int ret;
priv->sync_kernel = false;
if (!priv->armclk_enter_hz) {
priv->armclk_enter_hz =
rockchip_pll_get_rate(&rk1808_pll_clks[APLL],
priv->cru, APLL);
priv->armclk_init_hz = priv->armclk_enter_hz;
}
if (rockchip_pll_get_rate(&rk1808_pll_clks[APLL], if (rockchip_pll_get_rate(&rk1808_pll_clks[APLL],
priv->cru, APLL) != APLL_HZ) { priv->cru, APLL) != APLL_HZ) {
ret = rk1808_armclk_set_clk(priv, APLL_HZ); ret = rk1808_armclk_set_clk(priv, APLL_HZ);
if (ret < 0) if (ret < 0)
printf("%s failed to set armclk rate\n", __func__); printf("%s failed to set armclk rate\n", __func__);
priv->armclk_init_hz = APLL_HZ;
} }
priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL],
@ -1090,6 +1098,8 @@ static int rk1808_clk_probe(struct udevice *dev)
ret = clk_set_defaults(dev); ret = clk_set_defaults(dev);
if (ret) if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret); debug("%s clk_set_defaults failed %d\n", __func__, ret);
else
priv->sync_kernel = true;
return 0; return 0;
} }
@ -1165,6 +1175,7 @@ U_BOOT_DRIVER(rockchip_rk1808_cru) = {
int soc_clk_dump(void) int soc_clk_dump(void)
{ {
struct udevice *cru_dev; struct udevice *cru_dev;
struct rk1808_clk_priv *priv;
const struct rk1808_clk_info *clk_dump; const struct rk1808_clk_info *clk_dump;
struct clk clk; struct clk clk;
unsigned long clk_count = ARRAY_SIZE(clks_dump); unsigned long clk_count = ARRAY_SIZE(clks_dump);
@ -1179,7 +1190,14 @@ int soc_clk_dump(void)
return ret; return ret;
} }
printf("CLK:"); priv = dev_get_priv(cru_dev);
printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
priv->sync_kernel ? "sync kernel" : "uboot",
priv->armclk_enter_hz / 1000,
priv->armclk_init_hz / 1000,
priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
priv->set_armclk_rate ? " KHz" : "N/A");
for (i = 0; i < clk_count; i++) { for (i = 0; i < clk_count; i++) {
clk_dump = &clks_dump[i]; clk_dump = &clks_dump[i];
if (clk_dump->name) { if (clk_dump->name) {
@ -1193,17 +1211,17 @@ int soc_clk_dump(void)
clk_free(&clk); clk_free(&clk);
if (i == 0) { if (i == 0) {
if (rate < 0) if (rate < 0)
printf("%s %s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%s %lu KHz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000); rate / 1000);
} else { } else {
if (rate < 0) if (rate < 0)
printf("%s %s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%s %lu KHz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000); rate / 1000);
} }
} }