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rockchip: clk: Add rk322x bus pclk clock support 

Change-Id: I63fcd3527ac2d4447b0f49f4665ca99caa90d6e5
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
This commit is contained in:
Zhangbin Tong 2017-10-13 11:52:39 +08:00
parent c634813016
commit eecd6f34ae
1 changed files with 26 additions and 0 deletions
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26
drivers/clk/rockchip/clk_rk322x.c
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@ -314,6 +314,29 @@ static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
return set_rate;
}
static ulong rk322x_get_bus_aclk(struct rk322x_cru *cru, ulong gclk_rate)
{
u32 con;
u32 aclk_div;
con = readl(&cru->cru_clksel_con[0]);
aclk_div = ((con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT) + 1;
return gclk_rate / aclk_div;
}
static ulong rk322x_get_bus_pclk(struct rk322x_cru *cru, ulong gclk_rate)
{
u32 con;
u32 pclk_div;
con = readl(&cru->cru_clksel_con[1]);
pclk_div = ((con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT) + 1;
return rk322x_get_bus_aclk(cru, gclk_rate) / pclk_div;
}
static ulong rk322x_clk_get_rate(struct clk *clk)
{
struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
@ -330,6 +353,9 @@ static ulong rk322x_clk_get_rate(struct clk *clk)
case SCLK_SDMMC:
rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break;
case PCLK_GPIO0 ... PCLK_TIMER:
rate = rk322x_get_bus_pclk(priv->cru, gclk_rate);
break;
default:
return -ENOENT;
}