drm/rockchip: Support drm dw-hdmi
Add drm hdmi refer to kernel. Support Synopsys PHY HDMI, RK3399 has been tested. Change-Id: Iaae35ff15333cd1082149e016157c66ec3a6f3a6 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This commit is contained in:
Algea Cao
Kever Yang
parent
21016d27c5
commit
f5e7d25111
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@ -15,6 +15,14 @@ config DRM_ROCKCHIP_PANEL
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config DRM_ROCKCHIP_DSI_PANEL
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bool
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config DRM_ROCKCHIP_DW_HDMI
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bool "Rockchip specific extensions for Synopsys DW HDMI"
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depends on DRM_ROCKCHIP
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help
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This selects support for Rockchip SoC specific extensions
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for the Synopsys DesignWare HDMI driver. If you want to
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enable HDMI on, you should selet this option.
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config DRM_ROCKCHIP_MIPI_DSI
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bool
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@ -11,6 +11,8 @@ obj-y += rockchip_display.o rockchip_crtc.o rockchip_phy.o \
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obj-$(CONFIG_DRM_ROCKCHIP_MIPI_DSI) += rockchip_mipi_dsi.o
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obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += rockchip-dw-mipi-dsi.o \
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rockchip-inno-mipi-dphy.o rockchip_dsi_panel.o
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obj-$(CONFIG_DRM_ROCKCHIP_DW_HDMI) += rockchip_dw_hdmi.o dw_hdmi.o
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obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += rockchip-dw-mipi-dsi.o rockchip-inno-mipi-dphy.o
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obj-$(CONFIG_DRM_ROCKCHIP_ANALOGIX_DP) += rockchip_analogix_dp.o rockchip_analogix_dp_reg.o
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obj-$(CONFIG_DRM_ROCKCHIP_LVDS) += rockchip_lvds.o
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obj-$(CONFIG_DRM_ROCKCHIP_PANEL) += panel_simple.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,184 @@
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/*
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm/device.h>
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#include <linux/dw_hdmi.h>
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#include "rockchip_display.h"
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#include "rockchip_crtc.h"
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#include "rockchip_connector.h"
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#include "dw_hdmi.h"
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#include "rockchip_dw_hdmi.h"
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#define HDMI_SEL_LCDC(x, bit) ((((x) & 1) << bit) | (1 << (16 + bit)))
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#define RK3288_GRF_SOC_CON6 0x025C
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#define RK3288_HDMI_LCDC_SEL BIT(4)
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#define RK3399_GRF_SOC_CON20 0x6250
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#define RK3399_HDMI_LCDC_SEL BIT(6)
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static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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30666000, {
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{ 0x00b3, 0x0000 },
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{ 0x2153, 0x0000 },
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{ 0x40f3, 0x0000 },
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},
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}, {
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36800000, {
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{ 0x00b3, 0x0000 },
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{ 0x2153, 0x0000 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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46000000, {
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{ 0x00b3, 0x0000 },
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{ 0x2142, 0x0001 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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61333000, {
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{ 0x0072, 0x0001 },
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{ 0x2142, 0x0001 },
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{ 0x40a2, 0x0001 },
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},
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}, {
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73600000, {
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{ 0x0072, 0x0001 },
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{ 0x2142, 0x0001 },
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{ 0x4061, 0x0002 },
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},
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}, {
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92000000, {
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{ 0x0072, 0x0001 },
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{ 0x2145, 0x0002 },
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{ 0x4061, 0x0002 },
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},
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}, {
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122666000, {
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{ 0x0051, 0x0002 },
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{ 0x2145, 0x0002 },
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{ 0x4061, 0x0002 },
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},
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}, {
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147200000, {
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{ 0x0051, 0x0002 },
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{ 0x2145, 0x0002 },
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{ 0x4064, 0x0003 },
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},
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}, {
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184000000, {
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{ 0x0051, 0x0002 },
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{ 0x214c, 0x0003 },
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{ 0x4064, 0x0003 },
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},
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}, {
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226666000, {
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{ 0x0040, 0x0003 },
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{ 0x214c, 0x0003 },
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{ 0x4064, 0x0003 },
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},
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}, {
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272000000, {
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{ 0x0040, 0x0003 },
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{ 0x214c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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340000000, {
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{ 0x0040, 0x0003 },
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{ 0x3b4c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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600000000, {
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{ 0x1a40, 0x0003 },
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{ 0x3b4c, 0x0003 },
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{ 0x5a64, 0x0003 },
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},
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}, {
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~0UL, {
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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},
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}
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};
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static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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600000000, { 0x0000, 0x0000, 0x0000 },
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}, {
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~0UL, { 0x0000, 0x0000, 0x0000},
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}
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};
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static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
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/*pixelclk symbol term vlev*/
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{ 74250000, 0x8009, 0x0004, 0x0272},
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{ 165000000, 0x802b, 0x0004, 0x0209},
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{ 297000000, 0x8039, 0x0005, 0x028d},
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{ 594000000, 0x8039, 0x0000, 0x019d},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static const struct rockchip_connector_funcs rockchip_dw_hdmi_funcs = {
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.init = rockchip_dw_hdmi_init,
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.deinit = rockchip_dw_hdmi_deinit,
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.prepare = rockchip_dw_hdmi_prepare,
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.enable = rockchip_dw_hdmi_enable,
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.disable = rockchip_dw_hdmi_disable,
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.get_timing = rockchip_dw_hdmi_get_timing,
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.detect = rockchip_dw_hdmi_detect,
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.get_edid = rockchip_dw_hdmi_get_edid,
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};
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static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
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.vop_sel_bit = 4,
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.grf_vop_sel_reg = RK3288_GRF_SOC_CON6,
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.dev_type = RK3288_HDMI,
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};
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static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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.vop_sel_bit = 6,
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.grf_vop_sel_reg = RK3399_GRF_SOC_CON20,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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.dev_type = RK3399_HDMI,
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};
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static const struct rockchip_connector rk3399_dw_hdmi_data = {
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.funcs = &rockchip_dw_hdmi_funcs,
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.data = &rk3399_hdmi_drv_data,
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};
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static const struct rockchip_connector rk3288_dw_hdmi_data = {
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.funcs = &rockchip_dw_hdmi_funcs,
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.data = &rk3288_hdmi_drv_data,
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};
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static int rockchip_dw_hdmi_probe(struct udevice *dev)
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{
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return 0;
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}
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static const struct udevice_id rockchip_dw_hdmi_ids[] = {
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{
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.compatible = "rockchip,rk3399-dw-hdmi",
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.data = (ulong)&rk3399_dw_hdmi_data,
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}, {
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.compatible = "rockchip,rk3288-dw-hdmi",
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.data = (ulong)&rk3288_dw_hdmi_data,
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}, {}
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};
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U_BOOT_DRIVER(rockchip_dw_hdmi) = {
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.name = "rockchip_dw_hdmi",
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.id = UCLASS_DISPLAY,
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.of_match = rockchip_dw_hdmi_ids,
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.probe = rockchip_dw_hdmi_probe,
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};
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@ -0,0 +1,22 @@
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/*
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ROCKCHIP_DW_HDMI_REG_H_
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#define _ROCKCHIP_DW_HDMI_REG_H_
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/*
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* Rockchip connector callbacks.
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* If you want to know the details, please refer to rockchip_connector.h
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*/
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int rockchip_dw_hdmi_init(struct display_state *state);
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void rockchip_dw_hdmi_deinit(struct display_state *state);
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int rockchip_dw_hdmi_prepare(struct display_state *state);
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int rockchip_dw_hdmi_enable(struct display_state *state);
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int rockchip_dw_hdmi_disable(struct display_state *state);
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int rockchip_dw_hdmi_get_timing(struct display_state *state);
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int rockchip_dw_hdmi_detect(struct display_state *state);
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int rockchip_dw_hdmi_get_edid(struct display_state *state);
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#endif /* _ROCKCHIP_DW_HDMI_REG_H_ */
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