qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rockchip: rk3568: Enable FSPI secure 

Change-Id: Id46debc74bfac7060244079582b06b35817b51cd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin 2021-01-19 09:16:38 +08:00 committed by Dingqiang Lin
parent 7862d7bff3
commit f7a0277a1d
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-rockchip/rk3568/rk3568.c
View File

@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CRU_SOFTRST_CON26 0x468 #define CRU_SOFTRST_CON26 0x468
#define CRU_SOFTRST_CON28 0x470 #define CRU_SOFTRST_CON28 0x470
#define SGRF_BASE 0xFDD18000 #define SGRF_BASE 0xFDD18000
#define SGRF_SOC_CON3 0xC
#define SGRF_SOC_CON4 0x10 #define SGRF_SOC_CON4 0x10
#define PMUGRF_SOC_CON15 0xfdc20100 #define PMUGRF_SOC_CON15 0xfdc20100
#define CPU_GRF_BASE 0xfdc30000 #define CPU_GRF_BASE 0xfdc30000
@ -814,6 +815,11 @@ int arch_cpu_init(void)
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
#if defined(CONFIG_ROCKCHIP_SFC)
/* Set the fspi to secure */
writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
#endif
#ifndef CONFIG_TPL_BUILD #ifndef CONFIG_TPL_BUILD
/* set the fspi d0 cs0 to level 1 */ /* set the fspi d0 cs0 to level 1 */
if (get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NOR || if (get_bootdev_by_brom_bootsource() == BOOT_TYPE_SPI_NOR ||