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misc: otp: support rockchip secure otp version 2 driver 

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I10a8cc92f2130c1f1957fd36fb924d9846707e65
This commit is contained in:
Jason Zhu 2020-04-20 15:53:22 +08:00 committed by Jianhong Chen
parent 5b7d32987c
commit f9519410b1
4 changed files with 6727 additions and 0 deletions
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6
drivers/misc/Kconfig
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@ -86,6 +86,12 @@ config SPL_ROCKCHIP_SECURE_OTP
help help
Support read & write secure otp in spl. Support read & write secure otp in spl.
config SPL_ROCKCHIP_SECURE_OTP_V2
bool "Rockchip Secure OTP Version 2 Support in spl"
depends on SPL_MISC
help
Support read & write secure otp in spl. Support platforms: rv1126.
config CMD_CROS_EC config CMD_CROS_EC
bool "Enable crosec command" bool "Enable crosec command"
depends on CROS_EC depends on CROS_EC

1
drivers/misc/Makefile
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@ -54,5 +54,6 @@ obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rockchip-secure-otp.o obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rockchip-secure-otp.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP_V2) += rockchip-secure-otp-v2.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += misc_decompress.o obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += misc_decompress.o

6660
drivers/misc/rockchip-secure-otp-v2.S Normal file
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File diff suppressed because it is too large Load Diff

60
include/rockchip-otp-v2.h Normal file
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@ -0,0 +1,60 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#ifndef _ROCKCHIP_OTP_V2_H_
#define _ROCKCHIP_OTP_V2_H_
#define NVM_CEB 0x00
#define NVM_RSTB 0x04
#define NVM_TCSRST 0x08
#define NVM_TCEW 0x0c
#define NVM_TRW 0x10
#define NVM_TRS 0x14
#define NVM_ST 0x18
#define NVM_RADDR 0x1c
#define NVM_RSTART 0x20
#define NVM_RDATA 0x24
#define NVM_TRWH 0x28
#define NVM_TREW 0x2c
#define NVM_READ_ST 0x30
#define NVM_PRADDR 0x34
#define NVM_PRLEN 0x38
#define NVM_PRDATA 0x3c
#define NVM_FAILTIME 0x40
#define NVM_PRSTART 0x44
#define NVM_PRSTATE 0x48
#define NVM_PRSUCCESS 0x4c
#define NVM_TAS 0x50
#define NVM_TWWL 0x54
#define NVM_TDLEH 0x58
#define NVM_TDPD 0x5c
#define NVM_TPES 0x60
#define NVM_TCPS 0x64
#define NVM_TPW 0x68
#define NVM_TCPH 0x6c
#define NVM_TPEH 0x70
#define NVM_TPTPD 0x74
#define NVM_TPGMAS 0x78
#define OTPC_INT_ST 0x7c
#define NVM_INT_EN 0x80
#define OTP_PROG_MASK_BASE 0x0200
#define OTP_READ_MASK_BASE 0x0300
#define OTP_MASK_BYPASS 0x0400
#define OTP_MASK_INT_CON 0x0404
#define OTP_MASK_INT_STATUS 0x0408
#define OTP_MASK_STATUS 0x040C
#define OTP_MASK_PROG_LOCK 0x0410
#define OTP_MASK_READ_LOCK 0x0414
#define OTP_MASK_BYPASS_LOCK 0x0418
#define OTP_SLICE_LOCK 0x041c
#define OTP_SLICE 0x0420
struct rockchip_otp_v2_platdata {
void __iomem *base;
unsigned long secure_conf_base;
};
#endif