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rockchip: rk3066: enable early back to bootrom like rk3188 

We don't need tpl for rk3066 after we enable this option.
NOTE: need to update code for clock init in boot0 later

Change-Id: I253e6a0fd3633d982ebabaa045a0d4839570bc6a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2018-01-20 21:51:51 +08:00
parent e8078e9068
commit ffb06671e6
2 changed files with 1 additions and 90 deletions
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1
arch/arm/mach-rockchip/Kconfig
View File

@ -41,6 +41,7 @@ config ROCKCHIP_RK3066
select TPL
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
help
The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
including NEON and GPU, Mali-400 graphics, several DDR3 options

90
arch/arm/mach-rockchip/rk3066-board-tpl.c
View File

@ -1,90 +0,0 @@
/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <clk.h>
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr_rk3188.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rk3066.h>
#include <asm/arch/pmu_rk3188.h>
DECLARE_GLOBAL_DATA_PTR;
#define RK3066_TIMER_CONTROL 0x8
#define GRF_BASE 0x20008000
static int setup_arm_clock(void)
{
struct udevice *dev;
struct clk clk;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ret;
clk.id = CLK_ARM;
ret = clk_request(dev, &clk);
if (ret < 0)
return ret;
ret = clk_set_rate(&clk, 600000000);
clk_free(&clk);
return ret;
}
void board_init_f(ulong dummy)
{
struct rk3066_grf * const grf = (void *)GRF_BASE;
struct udevice *dev;
int ret;
/* Enable early UART on the RK3066 */
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B0_MASK,
GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
debug_uart_init();
printascii("U-Boot TPL board init\n");
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
/* Reset and enable Timer0 */
writel(0, CONFIG_SYS_TIMER_BASE);
rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1, 0x1);
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
setup_arm_clock();
}
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}