93a7515a89
video/rk_eink: add rockchip eink support.
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Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: I39e92ee00690ea1be274b1abd94d54284ef36898
2020-12-10 17:51:14 +08:00
0a04fb5062
clk: rockchip: rk3568: support rkvdec clk setting
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Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-10 15:26:42 +08:00
a792c7e0c5
mtd: spinand: Support new devices
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HYF1GQ4UDACAE, HYF4GQ4UAACBE
Change-Id: I7abcc925ccdf8be5507a8b584b58c6b03a78962c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:55 +08:00
4cab706e7f
mtd: spinand: Support new devices
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FM25S01
Change-Id: I1c7eab8799b0a381b7fa32584e608c3a115d83e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:48 +08:00
0659623d62
mtd: spinand: Support new devices
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FS35ND02G-S3Y2, FS35ND04G-S2Y2
Change-Id: Idc74c823fc707ba4dbeac359c4f6ca0a7e3ee778
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:34 +08:00
ad6355f7d7
mtd: spinand: Support new devices
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XT26G01C
Change-Id: If7147ebd12a993de86b335824d8c6e9d8ea06d52
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 16:00:38 +08:00
266cba03bb
mtd: spinand: Supoprt new devices
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TC58CVG2S0HRAIJ
Change-Id: I4412a9208fe8f22053dbb74d1cb362b19e13a18a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 15:07:38 +08:00
55efc32aea
mtd: spinand: Supoprt new MXIC devices
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MX35UF1GE4AC, MX35UF2GE4AC
Change-Id: I064e9116c565e2ea3b92432e9c68864d47a7567c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 14:57:38 +08:00
5fe488ff12
mtd: spinand: Support new devices
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HYF2GQ4UAACAE, HYF2GQ4UHCCAE
Change-Id: I1b36ca507984d2794375a6c1bce409d749495c62
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 14:53:06 +08:00
990fd51c55
misc: rockchip-otp: extract the difference in each chips
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We use function spl_rockchip_otp_start & spl_rockchip_otp_stop to
realize the different of each chip's otps, such as mask area and
secure config.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3b5d0377d78e5c2ed6e8ed52a89cadefc4994be1
2020-12-08 17:37:39 +08:00
3b02c9fe3a
power: fg_cw201x: replace fdt functions
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Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Id03c367e619444f5f76ecbb36f831e09959d2888
2020-12-07 02:34:36 +00:00
77e56285c1
clk: rockchip: rk3568: support set sdmmc0 clock
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Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic7bdfce9a9551649e053f58b6d9219e73e6afed5
2020-12-07 09:24:24 +08:00
f6d2779458
clk: rockchip: rk3568: support more clk setting
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support cpll_xxx settings.
Change-Id: I2735f6abe0fb02828b7ace76b58a60757199cab8
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
2020-12-07 09:22:55 +08:00
d62fa58224
mmc: sdhci: rockchip: reset the clock phase
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Reset the clock phase when the frequency is lower than 52MHz.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I49c50779ab5e1103d815cd2be1a7c9603cea397a
2020-12-07 09:20:43 +08:00
3c70338210
rkflash: Support new spinor
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1.Support XT25F256BSFIGU, P25Q32SH-SSH-IT
2.Fix PUYA devices property
Change-Id: I6c5ff381770508962f8ed16189d03385f511d84f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
a097a4fc3a
rkflash: Support spinor prog_addr_lines
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Convenient for spinor detection
Change-Id: Id9e09de26ffa978f18a97d8f0555c70ee0baa22c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
49eba1a38a
rkflash: Support sfc DLL api
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Change-Id: Ibe8cd0d1e72e8dc871466dcb1014e6817b184e80
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
b3621a1078
spl: zftl: fix L04A and L05B boot fail issue
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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icdc93ce7d8948c3c12f28aef08c98df4b3aa3166
2020-12-03 15:08:50 +08:00
84dc46da6a
drivers: rknand: update nand flash drivers
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1. support samsung 14nm 8GB NAND FLASH.
2. support ymtc 64L 32GB NAND FLASH.
3. support toshiba 15nm 8GB NAND FLASH.
4. support rk3568
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I01c9eb698c1ae829e6a2858c2664d62cf0851ab7
2020-11-30 10:03:05 +08:00
e18e709024
drivers: rknand: add nand flash drivers for spl
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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I21c449226f57f2ff05fdcf241dde014062634cb5
2020-11-27 20:06:23 +08:00
d7965d03e2
pinctrl: rockchip: add SPL support
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CONFIG_OF_LIVE is always available in SPL and U-Boot.
Use CONFIG_IS_ENABLED(OF_LIVE) to unwind as CONFIG_OF_LIVE
in U-Boot and CONFIG_SPL_OF_LIVE in SPL.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I980579d54850ca7655b464688ba9e6bd35f24250
2020-11-27 14:05:18 +08:00
038c1ecaa2
power: charge animation: energy enough auto exit uboot charge
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Change-Id: Ifa94783869c7cb35f819f3700c82bac7d00a7b05
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
2020-11-26 15:23:46 +08:00
00d11ef213
pmic: rk8xx: support power key config from dts
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Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I4b2def4e5b171b2b46f26695e9cabec8a7b496e2
2020-11-26 11:51:28 +08:00
e336ce4ee5
mtd: spinand: Add foresee devices
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Change-Id: I115ea19030edc2e83e877621f055555b481f98db
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-26 09:10:57 +08:00
65bd598f41
clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl
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Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5
2020-11-24 17:13:18 +08:00
00fa57d80d
driver: crypto: mask CRYPTO_SYNC_LOCKSTEP_INT_ST flag
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This flag maybe abnormal trigger.
Change-Id: Id398d1e8636c28b8cc42d950cafa5e2731a41b62
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2020-11-24 16:02:35 +08:00
7eea182341
crypto: rockchip: support rk3568 without hwrng in crypto
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Change-Id: I557a05e0336fe6b80d903a48a2d088f165a4eeca
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2020-11-24 16:02:35 +08:00
7ef28ab639
i2c: rockchip: Clean ipd status if i2c transfer error
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If there was an i2c transfer error like iomux error,
should clean the ipd status, it might cause kernel i2c
irq error handing.
[ 0.690749] rk3x-i2c fdd40000.i2c: irq in STATE_IDLE, ipd = 0x10
Change-Id: Ia127edada535288e9b984d6dc0dff813e6152eff
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-24 14:43:46 +08:00
22edf95882
mtd: spinand: Support W25N02KV
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Change-Id: Iaf4a50ce7bb0bb9978a05d339a34763445c09c84
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-20 20:54:39 +08:00
b833c879cf
rkflash: Support new spi flash
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1.Support W25N02KVZEIR
2.Support GD25B512MEYIG, MX25U51245G
Change-Id: Ia0181aa3fc6cbf17e2b0abd43dea80b5d9848d88
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-20 20:31:21 +08:00
dbff1ed621
gpio: rockchip: get gpio bank from pinctrl device
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Change-Id: I0dd2bc1b61bfdfe8edfd79b3a794522499eaae5c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
e9c98b3baf
gpio: rockchip: fix get gpio mux operation error return
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Change-Id: Ia225ae3acea2d2d2347870b3d6a20c4a7d22e7e9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
8273b391c5
pinctrl: rockchip: a pin unrouted is invalid
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Change-Id: I706b23277f33768fc7c8bcfd06e6417fe3e8a0db
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
fdd74c3220
clk: rockchip: rk3568: support ebc clk setting/getting rate
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Change-Id: Iecac8e56b2b5615b54c8969767053b6282fe6fb8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-19 14:48:18 +08:00
661bcdfeff
mtd: mtd_blk: add mtd_blk_map_fit() to create map for fit image
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Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I0d0195f455ee9afb32676510fc077fe63ae5c7ad
2020-11-18 16:10:55 +08:00
379e9cabde
drivers: ram: rk3308: add sdram_rk3308.c build
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Change-Id: I43079e6709d6eeb691eb73786bba7920c081b9c9
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-17 20:56:28 +08:00
b85730d9e9
clk: rockchip: rv1126: Fix mask bits for gmac src clks
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7f81a3e7586dcb85511502d3a329ac1cba7ccc8a
2020-11-17 14:46:27 +08:00
8ec8d58eeb
drivers: ram: rockchip: add rk3308 sdram driver
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Change-Id: I96160af2095ba21b440c6d3789349d8cbc4fea75
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-16 20:40:52 +08:00
b86c816ccb
drivers: ram: rockchip: rv1108: clean up the code
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Change-Id: I3446805fd9c320ddd49b9cb12df82943057ed9ee
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-16 20:39:39 +08:00
7329ce5782
phy: rockchip-inno-usb2: fix some issues for rk3568 usb2 phy
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This patch fixes the following issues for rk3568 usb2 phy.
1. Set utmi opmode to normal mode for rk3568 usb phy when usb
phy enter suspend mode via usb phy grf. It can help to avoid
the DM/DP floating and the line state be detected as 2'b11.
2. Fix the offset of INT_STATUS_CLR. It can help to avoid
triggering the linestate irq constantly.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ic108e116d1473341b61743ec4244bc034a95f501
2020-11-16 15:59:44 +08:00
802c460a72
clk: rockchip: rk3568: support ppll setting 200M
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Change-Id: If5d4d1994956a8e18f3208a22daee6efca80950b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-16 15:05:05 +08:00
458cbae45a
power: rockchip-io-domain: Use private write for rk3568
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The i2c5 xfer went wrong because of io-domain was not right
and was configured correctly in uboot to ensure that kernel
was right before initializing the io-domain driver.
Change-Id: Ic2f94952f7a851dc5b781af9f31bba2562b5a2b5
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-16 11:45:51 +08:00
8db677370c
irq: irq-gpio-switch: add gpio alias name support
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Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.
But from RK3568, we add gpio alias to indicate gpio index
information and index is removed from gpio node name, ie:
gpio@fdd60000, gpio@fe740000, etc.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I56e45941f9572fbc6a5a5916896e12f6eff9dcf3
2020-11-14 15:32:03 +08:00
e4e3f4318d
net: gmac_rockchip: Add rmii support for rv1126
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Change-Id: I89401b89ff8fd3d9cca754d6f1c05dc76ef2cda6
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-14 15:23:48 +08:00
3b2dd5de37
usb: dwc3: do not use 3.0 clock when operating in 2.0 mode
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In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.
Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-14 12:05:13 +08:00
60238d95dc
mmc: sdhci: rockchip: change tapnum to 16
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According to the test hadware testing.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I2750a7de9f79807256800868ae53d3fe4a23b2f1
2020-11-14 11:55:39 +08:00
007849d805
drivers: rockusb: add new idb feature for rk3568
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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iee5ed01bb336a5b5994381fc8e734da3b87329fe
2020-11-12 20:12:17 +08:00
8d74d6b7d3
drivers: mmc: rockchip: rk3568: config rx clock no inverter for hs200
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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I426a5c3ee0899fbd54711e13550310f77f8abd3e
2020-11-11 19:48:46 +08:00
fcff2851be
power: io-domain: rockchip: fix rk3568 grf offset
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Change-Id: I1045ce0d942ea57e325bdf3b8aa4bc8c9023d9e8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 17:15:52 +08:00
836c6892fa
pinctrl: rockchip: fix RK3568 for pull set
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Change-Id: I9fa739d65caf54067f8c61142ced44f9ad9d7313
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 17:15:52 +08:00
Wenping Zhang
Elaine Zhang
Jon Lin
Jason Zhu
Shunqing Chen
Yifeng Zhao
Joseph Chen
Lin Jinhan
David Wu
Jianqun Xu
Zhihuan He
Finley Xiao
Ren Jianing
William Wu