Find the first useful block in the end, and it is the end of
the nand storage.
Change-Id: I83203cbd764b2a6a6baa69694407f75339f176d5
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Since func nand_read_skip_bad is used in uboot, so just build it in
uboot build. And use func mtd_read to replace it.
Change-Id: Ic5e161f7f03cd2da0099891812360af67a2b9db8
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Since mtd_read() can not skip bad block if meet bad block, so use
nand_read_skip_bad().
Change-Id: Ic2364b7f29de193412353fad36c86dc6e289e02d
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
In the nand mtd, we will use chip info to operate nand, and get the chip
through mtd_to_nand(). So we should get mtd through dev_get_priv() but not
dev_get_uclass_platdata.
Change-Id: I1bacbec49158d04dc947a880dbe3a8043fe3123d
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Change-Id: I44522b3af6f28b74e0cdaf249edae6189e261a3e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a430fa06a4ac50e785fdbfb7f43c3cb14b35619c)
When ENV_IS_IN_UBI is enable, get_mtdparts is called before relocation.
During first get_mtdparts() call, mtdparts is not available in environment,
it can be retrieved by calling board_mtdparts_default(), but following
env_set() do nothing as we are before relocation. Finally mtdparts is
still not available in environment.
At second get_mtdparts() call, use_defaults is false, but mtdparts is still
not in environment and is NULL.
Remove use_defaults bool, only mtdparts criteria is useful.
Fixes: commit 5ffcd50612f6 ("mtd: Use default mtdparts/mtids when not defined
in the environment")
Change-Id: I5e789575c70c88fce758f36343baca7625afd297
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e6b7afe737f95f61f347a340acdda1a48d29ed50)
There is no 'config CRC32' remove the select that was attempting to use
it.
Change-Id: I5b21e1689cc2e98af4a24e8a0467935d7e90a215
Reported-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 661bbc50d3274ddc86245b8cd4a552956ccaffdf)
The support for DaVinci DM* SoCs has been dropped. The code that used
to be relevant to dm644x is no longer needed. Remove it.
Change-Id: I202b85f5f963d82dea73f0b7b88430134f00ba88
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a7fc3d7c687e4b7b61784ee7a13fd9e054a18e17)
Some SPI controllers can't write nor->page_size bytes in a single step
because their TX FIFO is too small, but when that happens we should
make sure a WRITE_EN command before each write access and READ_SR command
after each write access is issued.
We should allow nor->write() to return a size that is smaller than the
requested write size to gracefully handle this case.
Also, the spi_nor_write_data() should return the actual number of bytes
that were written during the spi_mem_exec_op() operation.
This patch is a combination of two commits backported from kernel:
commit 630d6bd8a3b4 ("mtd: spi-nor: Support controllers with limit ...")
commit 3baa8ec88c2f ("mtd: devices: m25p80: Make sure WRITE_EN is ...")
Cc: Vignesh R <vigneshr@ti.com>
Change-Id: I352142d4325b15c52eb04ac929b9e2bcd3648472
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Tested-by: Shyam Saini <shyam.saini@amarulasolutions.com> # microzed
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 60e2bf46784ebbd30ff29b3d3c7c97e56b11e86a)
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disabled the default layout when it was _not_ selected.
It breaks all the NAND drivers not providing their own ECC layout this
patch fix this situation.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Change-Id: I5bb978707782b690533152aaf71f34e10387fc6d
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5f626e78491c95dbf3e5036cc0c67aea8b1746fd)
The option write-protect may only change on the kernel command line,
we add a property in the device tree to be more flexible.
Change-Id: I9b09732a963f89571b723b66c62978aacf274a98
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f917438772c7c7da7f30e9209d9f100edac0255e)
The parameter page isn't always in big endian, so we add
an option to choose the endiannes of the parameter page.
Change-Id: I58c8ce2f6a2d4ac71c0b832a76e2ec5b943004e2
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 317d40eb01a8e194e6e321e71e811d6da03b8365)
The driver brcmnand come from linux kernel 4.18.
Only SoC bcm6838 and bcm6858 are supported.
Change-Id: I0337600b164da018c1236ef9cbdd90ecc0904ee7
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 22daafba25592b79112d21d1662d7b8381827c56)
Linux commit 97d90da8a88 ("mtd: nand: provide several helpers
to do common NAND operations")
This is part of the process of removing direct calls to ->cmdfunc()
outside of the core in order to introduce a better interface to execute
NAND operations.
Here we provide several helpers and make use of them to remove all
direct calls to ->cmdfunc(). This way, we can easily modify those
helpers to make use of the new ->exec_op() interface when available.
Change-Id: I721c476a3ea5997dd4e4ca68ed929543478efd69
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[miquel.raynal@free-electrons.com: rebased and fixed some conflicts]
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[Philippe Reynes: adapt code to u-boot and only keep new function]
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9db29b300f7d9a58122a22a0815fe8449a664563)
This adds reset handling to the devicetree-enabled Denali NAND driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Change-Id: I0d0ccb6e20f7c3ca6056c8aa03fb8ccd7b7bf340
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ed784ac3822b7d7019679a41a17907296e2dadbe)
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Change-Id: I30c2a61a49af2f8855f7f98ef302a70554d87a5d
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7bb75023a720432a32840c6df543aae92653b23d)
This adds support for the Gigadevice gd25lq128 ID needed on the
upcoming libretech-ac board.
SPI_NOR_QUAD_READ is not set since it has not been tested in Quad
mode.
Change-Id: If9b3b25e63bffbecff454dde94e5cb418a5d3cf6
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 30b9a28a3f2dc599dc9c6d6d6c015fb89bed95bf)
This patch update the behavior introduced by
commit 96907c0fe5 ("dm: spi: Read default speed and mode values from DT")
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_* but instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Remove also use in boards of the value speed=0 (no more supported)
for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0.
DT values will be always used when available (full DM support of
SPI slave with available DT node) even if speed and mode are requested;
for example in splash screen support (in splash_sf_read_raw)
or in SPL boot (in spl_spi_load_image).
The caller of spi_get_bus_and_cs() no more need to force speed=0.
But the current behavior don't change if the SPI slave is not
present (device with generic driver is created automatically)
or if platdata is used (CONFIG_OF_PLATDATA).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Change-Id: I6f5990b73f33815a7acb9b5da9c90dce48b6211d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b0cc1b846fcb310c0ac2f8cbeb4ed5947dc52912)
Replace the ad-hoc erase operation implementation with a simple spi_mem_op
implementation of the same functionality. This is a minor optimization and
removal of the ad-hoc code.
This however also changes the behavior of the execution of the erase
opcode from two separate transfer requests to the SPI NOR driver to
one transfer request to the SPI NOR driver. The former was how U-Boot
behaved before the SPI NOR framework was imported and the later was
introduced by the SPI NOR framework. The former is more optimal, so
keep that.
Change-Id: Ie8f39dff83fd7f49b606c813be0260a159257ac9
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
Tested-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f909ddb3e1770a5ef18606b46000e0d3eaf63b2e)
A Coverity robot reported an integer handling issue
(OVERFLOW_BEFORE_WIDEN) in the potentially overflowing expression:
(mtd_div_by_ws(mtd->size, mtd) - mtd_div_by_ws(offs, mtd)) *
mtd_oobavail(mtd, ops)
While such overflow will certainly never happen due to the numbers
handled, it is cleaner to fix this operation anyway.
The problem is that all the maths include 32-bit quantities, while the
result is stored in an explicit 64-bit value.
As maxooblen will just be compared with a size_t, let's change the
type of the variable to a size_t. This will not fix anything but will
clarify a bit the situation. Then, do an explicit cast to fix Coverity
warning.
Addresses-Coverity-ID: 184180 ("Integer handling issues")
Change-Id: Iab6b48d8709a7dcb70eebeb33088e866ee17dadf
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3f3aef4b9dc88278f31567fe6f26095fd9477b1a)
Add Macronix MX66U2G45F flash device description.
This is a 256 MiB part.
Change-Id: I3b546ca5a5268aa8fb0805ab6125242a724792d1
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Vignesh R <vigneshr@ti.com>
[jagan: use 'g' instead of 'f' in flash name]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3d2f12c4a151f6a4ec54782befa2fa92bcaa558f)
Now the "spi-flash" compatible has been removed in the DTS files,
remove this compatible from sf_probe to finally use the Linux "jedec,spi-nor"
compatible.
Change-Id: Iefd8098160529df04c9e7db2558bdf82117d095c
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit cd35365762add381b5765926f967d6a7259db783)
Add support for SPANSION s25fl064l
Change-Id: I081105625dcf484bd2c4d71080fc9c15f6df0ba7
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a2dc8b1832734fdd0c567dbaa1c8f98e10c427e2)
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support
with the latest Linux version (v5.0-rc3) plus the chip supported posted
on the MTD list. Only the currently in U-Boot available chip is
supported with this sync.
The changes for the GD5F1GQ4UExxG are:
- Name of NAND device changed to better reflect the real part
- OOB layout changed to only reserve 1 byte for BBT
- Use ECC caps 8bits/512bytes instead of 8bits/2048bytes
- Enhanced ecc_get_status() function to determine and report
a more fine grained bit error status
Change-Id: Ia0f8ea6e9c19aec57628ea3217128c389c1375c1
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d67fb265d1c071c6475fd97d01787b4c961516d5)
Before printk.h was introduced and MTDDEBUG was removed,
pr_crit() was calling MTDDEBUG(), which was since then
replaced by the current pr_debug().
pr_debug is more appropriate here.
Change-Id: Id553ff366acbb614f7a8adee6e8e46f79535be08
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 734b080e78805edbb3430a52c8c5b1aeee02bd9f)
Add a new definition for ubi_assert and keep
the original one in an ifndef __UBOOT__.
Change-Id: I73cb2a932ad46bffffdce86250d4e08940d0aed9
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 66e78fc196f59a9cd2688effa4d4d2eea32b0ed5)
Currently the spl system calls nand_init which does nothing.
It isn't until an attempt to load from NAND that it gets initialized.
Subsequent attempts to load just skip the initialization because
NAND is already initialized.
This moves the contents of mxs_nand_init to nand_init. In the event
of an error, it clears the number of nand chips found. Any
attempts to use nand will check if there are nand chips available
instead of actually doing the initialization at that time. If there
are none, it will return an error to the higher level calls.
Change-Id: Icfde060758de88354580fc4834adb880bb205b39
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d46d27d3b6558904b8fb44e90393f11c54ef3363)
The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others. With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank. This patch has been tested in NAND flash with oob 64
and oob 128.
Change-Id: Iaa9d322e8b39bbde309993e9bb9cb53cd920e80c
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 04568bd0b6d673a325eed76bd857a9cbd0c556bc)
mxs_nand_init_dma is only referenced from mxs_nand.c. It's not
referenced in any headers or outside code, so this patch
defines it as static.
Change-Id: I6c1dd1690288a073b95a715c53e4bc36b154dd59
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5645df9e00a01407730dc11d3a2bc4969203dc8c)
The LogicPD board uses a Micron Flash with ECC. To boot this from
SPL, the ECC needs to be correctly configured or the BCH engine
times out.
Change-Id: I0fcdc7f4853bf01c1a7318f4384767e9cb252e2c
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5ae585ba3a8bb2336d5cb6e1ef4c80a5ef445409)
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Change-Id: I9b87d3ed4a01d2ce31eee327b67689e5e2ecff57
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 778572d7cb1e2df678340fda9b081e4f7bd6c4b3)
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I4c459ebdff8b2aec38623f27d0ba630c6c6f1ca3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c4e8862308d420e85c227498797c32410d9e47a8)
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.
Change-Id: I4eea83ffe642240f398443bd73e6c331c64d3aac
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2ee6705be01c430ad9f71c0bac02d1d59819072c)
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Change-Id: I6888e49eeaeb89adca64cb8ca6683b27781bd7a8
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c927809ea960596345c33b02294af6e236d4ad4)
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I595586c8e491a56b6819182bc30de8e7f70b9476
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0c6f187cdb18b52bcf6d3964771cf3a36b758568)
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.
Change-Id: I051c17ed80e1b483166a3057732ae579cc2572c9
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 61059bc55ab108bdd53c953480b3f84f9d6100ab)
Jon Lin
Jason Zhu
Yifeng Zhao
Patrice Chotard
Chris Packham
Bartosz Golaszewski
Weijie Gao
Gregory CLEMENT
Philippe Reynes
Boris Brezillon
Simon Goldschmidt
Christophe Kerello
Neil Armstrong
Patrick Delaunay
Marek Vasut
Miquel Raynal
Marek Vasut
Heiko Schocher
Stefan Roese
Eran Matityahu
Adam Ford
Vignesh R