8d52d662b5
clk: rockchip: rk3288: Fix i2c clk rate calc
...
Change-Id: I083e2b8ceaa3eee7729174aa2e17b8a08cec9c05
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-01-13 09:00:50 +08:00
d504dfb2b1
clk: rockchip: rk3568: Ungate PCIe30phy refclk_m and refclk_n
...
Change-Id: I718f280cd78235131f3f3ef76e17e498a6e4db8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2021-01-07 10:00:59 +08:00
658285c1fb
clk: rockchip: rv1126: mux aclk_pdbus according to frequency
...
Aim to reduce power consumption, cpll should be gated and the clocks
will mux to non-cpll.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If9d1b48cdb237cf38133523a4fc20fa6e87e8e62
2020-12-31 14:39:56 +08:00
6c0e8ad896
clk: rockchip: rk3568: support wdt clk set/get rate
...
Change-Id: I04b868618f0590b44cea8c00041b9fb676e55919
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-28 16:19:25 +08:00
1abad17a96
clk: rockchip: rv1126: support wdt clk set/get rate
...
Change-Id: If47a22130507cb3512a8f19b474ea1e01354b52b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-28 16:19:25 +08:00
aa00306883
clk: rockchip: rk3568: fix up the return value for rk3568_clk_set_rate()
...
Change-Id: If472e1b954624ff5205e3064d484de3533cde949
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-24 15:11:20 +08:00
98637248d5
clk: rockchip: rk3568: fix print error log
...
The log is "Fail to set the ACLK_BUS clock"
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie22e5139e1446ae751d1e64729c7a0b4cdbac69e
2020-12-22 12:10:45 +08:00
0a04fb5062
clk: rockchip: rk3568: support rkvdec clk setting
...
Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-10 15:26:42 +08:00
77e56285c1
clk: rockchip: rk3568: support set sdmmc0 clock
...
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic7bdfce9a9551649e053f58b6d9219e73e6afed5
2020-12-07 09:24:24 +08:00
f6d2779458
clk: rockchip: rk3568: support more clk setting
...
support cpll_xxx settings.
Change-Id: I2735f6abe0fb02828b7ace76b58a60757199cab8
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
2020-12-07 09:22:55 +08:00
65bd598f41
clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl
...
Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5
2020-11-24 17:13:18 +08:00
fdd74c3220
clk: rockchip: rk3568: support ebc clk setting/getting rate
...
Change-Id: Iecac8e56b2b5615b54c8969767053b6282fe6fb8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-19 14:48:18 +08:00
b85730d9e9
clk: rockchip: rv1126: Fix mask bits for gmac src clks
...
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7f81a3e7586dcb85511502d3a329ac1cba7ccc8a
2020-11-17 14:46:27 +08:00
802c460a72
clk: rockchip: rk3568: support ppll setting 200M
...
Change-Id: If5d4d1994956a8e18f3208a22daee6efca80950b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-16 15:05:05 +08:00
801ca42bf6
clk: rockchip: rk3568: fix up the vpll register address
...
Fix up the error description of TRM.
Change-Id: Ie95482efea4e78505d361b5377ff4a23826d69e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-10 10:20:20 +08:00
d41e2874c4
clk: rockchip: rk3568: emmc support 52MHz
...
Change-Id: I54841ec5c7a5030bbbf9fa5b6b6fdc742250a127
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-08 20:28:41 +08:00
d01aebd267
clk: rockchip: rk3568: emmc support 400KHz
...
Change-Id: I1b16a4ad2e67749e63eb1506c6c1462db3e6abbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-08 19:15:43 +08:00
392d4cef34
clk: rockchip: rk3568: update the clk config
...
modify the cpll and gpll register.
support Hpll set/get rate.
Change-Id: I46b372078435bc70a34d1402d43ce2431110ddbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-10-26 16:25:37 +08:00
417bebc456
clk: rockchip: rk3568: Add clock driver
...
Add basic clock for rk3568 which including cpu, bus, mmc,
i2c, pwm, gmac ...clocks init.
Change-Id: I4119f10897d06befa4a39198b3724dc515d416e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-10-22 19:39:19 +08:00
c3723ef337
clk: rockchip: rk3399: support crypto clk set/get in SPL
...
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I159d062320ca523e8dc4f0dcce94a619692481f3
2020-10-22 16:37:49 +08:00
62be0c2c53
clk: rockchip: rk3368: support get pll config by table
...
add some special pll configs for better clock jitter.
Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-09-04 14:22:54 +08:00
446ef41c12
clk: rockchip: rv1126: always support decompress clock get/set
...
The SPL without thunder-boot or U-Boot needs it.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc910dae94419afcbfc09
2020-08-21 17:49:13 +08:00
7c7fff393f
clk: rockchip: rk3288: support get pll config by table
...
add some special pll configs for better clock jitter.
Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-20 15:09:48 +08:00
403d8d4c21
clk: rockchip: rk322x: add support to set and get spi clock
...
Change-Id: I361aa06aa795d2c041d2bdad9ee5ff6982d554fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
7f619f26d7
clk: rockchip: rk3128: add support to set and get spi clock
...
Change-Id: I4ac874ba0542474baf18491f986f401c831a5ad4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
df77e7a38c
clk: rockchip: rk3036: add support to set and get spi clock
...
Change-Id: I24db5f250fa89845b62005950d520600434adb99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
db5be31cab
clk: rockchip: rv1108: add support to set and get spi clock
...
Change-Id: I96891a4adb53bbb84e27cc0ac5eddf3c613c1baa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
514da3912b
clk: rockchip: rk3328: fix up the bus and peri aclk div overflow
...
Change-Id: I3983af87bec9bd79280914c803f0af3d5e3ffbb0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-05 15:52:38 +08:00
a9cbfff9cb
clk/rockchip: px30: support any frequency for i2s1_mclk
...
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ica0ca19d1a4fafbaf62e5c789ae3223ff9d86632
2020-07-30 14:59:32 +08:00
9936e5dd9c
clk: rockchip: px30: fix n/m for sclk_i2s1
...
High 16-bit for numerator, Low 16-bit for denominator.
Fixes: 95f2641240
2020-07-30 14:59:32 +08:00
d0999afb2e
clk: rockchip: rk3308: add support to set and get sfc clock
...
Change-Id: I322471da6e50b0bad328dde015d0d7d0466cc3a9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-06-03 09:57:07 +08:00
d47b686da8
clk: rockchip: rv1126: Add support to get dpll rate
...
Change-Id: Icd7c40235d4627befc216812bfdcb288790e63e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-06-03 09:56:37 +08:00
827e2ae92e
UPSTREAM: clk: add clk_valid()
...
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I78b1edea1f8ef54d3aa3f7610d39d79dd994d1bf
2020-06-02 16:07:42 +08:00
24f48ac9a8
clk: rockchip: rv1126: Change pclk pdbus parent to gpll
...
As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from
gpll.
Change-Id: Idd2f362fcf160352dcb4577ad8a13b4dbec7c65f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-06-02 11:01:58 +08:00
5410c5c273
clk: rockchip: rv1126: Add clock init for isp and vop
...
Change-Id: I1c4a1267e90f84f6f7777a35e0ad5824b6eff2d1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 17:44:27 +08:00
5ecc545e4e
clk: rockchip: rv1126: Add support for decom clock
...
Change-Id: I90eacb03ed191b804911429af5ad80daab3776cc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 17:44:27 +08:00
c17ccbf6fd
clk: rockchip: rv1126: Add support for isp and ispp clocks
...
Change-Id: Icfd87f56c30bfa81b6e7fecadcda090c26a8c465
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 17:44:27 +08:00
15ede2a15c
clk: rockchip: rk3036: Add support for vop
...
Change-Id: I0f057350a6ad07f61aaf42c84e50c452ee662f46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-14 16:42:38 +08:00
2438a166f4
clk: rockchip: rv1126: Add support for gmac
...
Change-Id: I10ade6acbbfe5dd23e33a250ef601948606bc57e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-11 11:31:56 +08:00
987a49158f
clk: rockchip: rv1126: Fix CLK_SCR1_CORE return error
...
Change-Id: I4938dd5519dde3a5357b5daf398d5915976ce74e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-04-17 16:49:50 +08:00
85967b2028
clk: rockchip: rv1126: Add PLL configuration for 1400MHz
...
The rate of HPLL is 1400MHz.
Change-Id: I225017f7fb461124c74939828aee4a2a40222097
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-04-17 14:55:32 +08:00
c637f2321b
Merge branch 'next-dev' into thunder-boot
...
Change-Id: I22ac688008080eac49169d752a94b66668f890fc
Conflicts:
drivers/phy/Kconfig
drivers/phy/Makefile
2020-04-16 15:48:00 +08:00
45d1e0c8a3
clk: rockchip: rk3399: add usb3.0 host clocks mandatory
...
This adds clocks mandatory for the DWC3 controllers of RK3399,
as these are enabled by default we just simply return success.
Change-Id: I81006d710cb6b4608c8dfa61a4eef661415bad29
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
2020-04-15 15:44:22 +08:00
56a06ac82e
clk: rockchip: rv1126: Add support to init hpll and 32k
...
Change-Id: If41a708d925c978e8db1e21b23c16d9a9a2e29d8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-04-14 20:09:21 +08:00
82c18007fb
clk: rockchip: rv1126: Modify divs for pll
...
There are some constraints for pll.
Input frequency range(Int): 5MHz to 1200MHz.
Input frequency range(Frac): 10MHz to 1200MHz.
Output frequency range: 16MHz to 6400MHz.
VCO frequency range: 1600MHz to 6400MHz.
Feedback divide(Int): 16 t0 640.
Feedback divide(Frac): 20 to 320.
Postdiv1 >= Postdiv2.
Change-Id: Ic8b8da6097f476597733984145056b6cc6cc453e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-04-14 12:41:51 +08:00
41bb8b737c
Merge branch 'next-dev' into thunder-boot
...
Conflicts:
common/spl/spl_rkfw.c
drivers/pinctrl/pinctrl-rockchip.c
make.sh
Change-Id: I93f4dbe1e067c3b938bf64c4964bd5e7023b1daf
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2020-04-07 21:18:08 +08:00
3732e2b8b1
clk: rockchip: rk1808: enable saradc in spl
...
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iaf91ec37624b3cd2dd7328ae8eb082236a40f83e
2020-04-04 10:55:58 +08:00
4d22530ea4
clk: rockchip: rv1126: Change CPLL to 500MHz
...
Make clk_gmac_ethernet_out2io 25MHz comes from CPLL.
Change-Id: Ie7f3bf457db8f92a5d75a0e5a78e5e61ffc7b0ac
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-04-02 19:58:05 +08:00
f8cddc3e74
clk: rockchip: rv1126: Add support for SCR1
...
Change-Id: I22f0cea9ab0612250ab41526684dc3d786555a37
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-03-30 09:43:42 +08:00
b865093666
clk: rockchip: rv1126: Change some clocks' parent to GPLL
...
Change-Id: Ibba02fee3df6c98308d5fd657a30af3eba7321d5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-03-26 09:13:26 +08:00
Wyon Bi
Shawn Lin
Ziyuan Xu
Elaine Zhang
Jason Zhu
Finley Xiao
Joseph Chen
Fabrice Gasnier
Frank Wang