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Author SHA1 Message Date
Finley Xiao 6224aca828 clk: rockchip: rv1126: Fix HCLK_PDPHP_DIV_SHIFT 
Change-Id: Ia30bcf94de7ee3e40359fdd47d4e8c6600f4559d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-03-26 09:13:26 +08:00
Joseph Chen 7497bc3dae Merge branch 'next-dev' into thunder-boot 
Change-Id: I35db1f0aa79575e972942b5c366f380fc8106343
 2020-03-13 17:49:04 +08:00
Elaine Zhang 904b267d4b clk: rockchip: rk3036: add nandc clk init 
Change-Id: I8aefe310a366e346310135f684f3b5db43b0b734
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2020-03-11 17:05:17 +08:00
Elaine Zhang ddf875ab3d clk: rockchip: rk3288: Reduce the hevc clock init frequency 
Solve the video clock high frequency reset problem.

Change-Id: I2db4021d8c20d572bda045256360f4e9bed9f85c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2020-03-11 14:39:41 +08:00
Finley Xiao 200899f92b clk: rockchip: rv1126: Don't restore clk when gpll is default 24MHz 
Change-Id: Ie7b2609078ae1b68fb8e081b4064381e3dbb36a8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-03-04 15:17:49 +08:00
Finley Xiao 0945879144 clk: rockchip: rv1126: Fix gpll_hz is zero when set gpll clk 
Change-Id: Iecd64e83d2a841b711c80528a245d2e9bda11265
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-03-04 15:17:49 +08:00
Finley Xiao ffe82b3398 clk: rockchip: rv1126: Remove unused local variable ret 
Change-Id: I2c4a056fd9fac2b50fd55a529133f7ea6f394437
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-03-04 15:17:49 +08:00
Joseph Chen 1a4f6af8bf Merge branch 'next-dev' into thunder-boot 2020-03-02 09:43:23 +08:00
Finley Xiao f96f01225f clk: rockchip: rv1126: Add support restore emmc/sfc/nandc frequency 
Change-Id: Iaa62eead12156d284a6ee315dfbaf92e786a0920
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-02-27 15:14:49 +08:00
Finley Xiao 57ae0852b1 clk: rockchip: rv1126: Add support for sfc and nandc 
Change-Id: Ifb6873bf417adaaf95703064deeaed54b890b20b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-02-27 11:40:36 +08:00
Elaine Zhang 9bc02da530 clk: rockchip: px30: Restore sfc frequency after PLL frequency setting 
Change-Id: I261885b027c4c5ba6d94fb228fb04563cb4e0b0e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2020-02-25 16:56:09 +08:00
Elaine Zhang c2fb06de29 clk: rockchip: rk1808: Restore mmc/sfc frequency after PLL frequency setting 
Change-Id: I14d0f9c41c45253de3a71b7c3d3fdae89ddf9952
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2020-02-24 18:09:37 +08:00
Jason Zhu 28e9e98a51 clk: rockchip: rk1808: set gpll to 594000000 
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.

Change-Id: Id356c87b1db158a0638e4560e886868f133dfaf9
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2020-02-24 14:03:43 +08:00
Joseph Chen f95775d6f3 clk: rockchip: rename rv1109 to rv1126 
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If2c870831fd1e3332c09f00aaa9e91a1f1523279
 2020-02-21 10:34:48 +08:00
Joseph Chen 243edbf940 clk: rockchip: rk3399: init 816 MHz for ARM big core 
We don't use clk_set_defaults() to initial it, because
there are too many clocks to be set in "assigned-clock-rates"
which wastes time.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6de5e2174945fdbce06e044c390ae2860970b0c4
 2020-01-10 10:51:42 +08:00
Finley Xiao 1bbed24709 clk: rockchip: rk3308: Add support to set and get clk_rtc32k clock 
Change-Id: Iea481af0c99a2b2ca9d6eff050e96e80845c8478
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-01-08 17:50:42 +08:00
Neil Armstrong 0afa4b6c53 UPSTREAM: clk: add sandbox test for bulk API 
This patch adds the bulk clock API tests for the sandbox test suite.

It's very similar to the main test but only uses the _bulk() API and
checks if the clocks are correctly enabled/disabled.

Change-Id: Ibfd7ea033e9a1c2ca76d88be8ca562a660f30448
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 65388d0dc5a36fc86718ffcdf08ac5671ae27b5d)
 2020-01-07 17:24:50 +08:00
Neil Armstrong 977da8af08 UPSTREAM: clk: Add get/enable/disable/release for a bulk of clocks 
This patch adds a "bulk" API to the clock API in order to get/enable/disable
/release a group of clocks associated with a device.

This bulk API will avoid adding a copy of the same code to manage
a group of clocks in drivers.

Conflicts:
	drivers/clk/clk-uclass.c

Change-Id: I7f992b206662bf5f931a835d98b3e3cd0f4347f1
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a855be87da49ba750e83ecc526235fe33099f76e)
 2020-01-07 17:24:50 +08:00
Finley Xiao 1f1e1246f6 clk: rockchip: rv1109: Add clock driver 
Add basic clock for rv1109 which including cpu, bus, emmc clock init.

Change-Id: I093f9e75bf296b3cc7f0ee8f88496e42857a2d96
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2019-12-11 15:07:24 +08:00
Elaine Zhang 20769c6481 clk: rockchip: rk1808: Restore crypto frequency after PLL frequency setting 
Change-Id: I4821309bfe1a2333469eae1d92f1d7716ea6635e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-12-10 11:30:51 +08:00
Yifeng Zhao 4333cc9aff rockchip: drivers: clk: rk3328: add spi clk config for spl and uboot 
Change-Id: I12da02d52e3c4aec64fbd6a378cd40e96c3775ce
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>
 2019-12-06 14:28:32 +08:00
Kever Yang f546c94580 rockchip: rk3288: no need to check PLL setting. 
Remove assert to make DEBUG work.

Change-Id: Idd41066f98c759b4fefe25c8715138c1c54df418
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-11-19 16:49:37 +08:00
Joseph Chen b8dc613cbc Merge branch 'next-dev' into thunder-boot 2019-11-19 16:15:43 +08:00
Jason Zhu a9f7ad7f11 clk: rockchip: rk1808: set gpll to 594000000 
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.

Change-Id: I28f56f161eb40cf640f7d979f53f8e6fdaff957c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2019-10-18 09:58:58 +08:00
Lin Jinhan a13a6cc2f5 clk: rockchip: rk3308: drop CONFIG_SPL_BUILD control rules 
Change-Id: Iba8a3cfcf201e10630211b1190bf9e95b04cf475
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2019-10-15 08:48:00 +08:00
Elaine Zhang e57a08e58f clk: rk3399: fix up the i2c clk error 
I2c MUx is in cpll by default, but cpll is for dclk_vop exclusive.
If dclk_vop set rate after i2c init, the CPLL changed,
but the i2c not perception, it will resulting the wrong frequency
of the i2c.
So set the i2c frequency according to the kernel configuration.
and Hang I2C on the GPLL.

Change-Id: I91f891e9033e9d4648027ea253998a54011f4863
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-09-27 15:01:34 +08:00
Elaine Zhang 667b42a84d clk: rockchip: rk3368: improve DCLK signal quality 
Improved PLL output jitter can support more types of 4K TV.

Change-Id: I40a81cc276abf6ca859ad91be6785ffd15747ee5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-09-10 14:09:49 +08:00
Jon Lin b491b49882 UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit 
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I638846de7db29711fb7c778cc8304b507de057fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 48263504c8d501678acaa90c075f3f7cda17c316)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2019-07-05 19:21:04 +08:00
Elaine Zhang 32f0452dd7 clk: rockchip: rk1808: support crypto clk get/set rate 
Change-Id: Id09bd7e6a303bc3e72421aeef277a16805e95761
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-07-03 09:34:10 +08:00
Elaine Zhang 88cae289b5 clk: rockchip: rk3368: support crypto clk get/set rate 
Change-Id: I736fdda1d994ebdb59c68f8be209bae0e206be99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-16 14:40:33 +08:00
Elaine Zhang 582fa222b9 clk: rockchip: rk3128: support crypto clk get/set rate 
Change-Id: I3a7d71a481aca04c9e6c0547cfc05a8106f79423
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-16 14:40:33 +08:00
Elaine Zhang f149c047e6 clk: rockchip: rk3036: fix up the assert error 
Change-Id: Id987e8847dbe97e5502259a9432dac85782769f3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-05 15:49:26 +08:00
Elaine Zhang 27b00bb2a4 clk: rockchip: rk3066: fix up the assert error 
Change-Id: I4d75bef4f1450e2cb467eb106b81e80eb8f582d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-05 15:49:22 +08:00
Elaine Zhang d177ad999c clk: rockchip: rk3188: fix up the assert error 
Change-Id: I690798cd9a17e266c32d702f5b2c8bfdc413d970
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-05 15:49:19 +08:00
Elaine Zhang a0af2ba7c7 clk: rockchip: rk3288: fix up the assert error 
Change-Id: I066a217b15108db21821c63bd7709fb430d34f45
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-05-05 15:49:14 +08:00
Elaine Zhang 88c36f1205 clk: rockchip: rk3399: fix up the assert error 
Change-Id: I8cc4f6b775243fef1f5c8e2c711eb1b16eac79a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-28 14:51:00 +08:00
Elaine Zhang 6b5ade5a57 clk: rockchip: rk1808: fix up the clk_set_default failed 
Change-Id: If49d6def0e16b93238311885217f30a4b7a2e7c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 12:04:10 +08:00
Elaine Zhang b9f5972251 clk: rockchip: rk1808: add mac clk interface 
support mac clk set rate and set parent.

Change-Id: I3b4626fd3fcc5ffdf3c58add9c1bc002bb56429a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 12:04:10 +08:00
Elaine Zhang 22d359b877 clk: rockchip: px30: add mac clk interface 
support mac clk set rate and set parent.

Change-Id: Iaadcb701cf37083d90a37b24f4ffba3bef9c88cd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 11:24:29 +08:00
Elaine Zhang 221585fb35 clk: rockchip: rk3308: support pclk_wdt get rate 
Change-Id: I001cfef774c9657b6286467dc4ef841771841895
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang ced960d2b6 clk: rockchip: rk3288: support pclk_wdt get rate 
Change-Id: I99f384344feb68ae5b91ade901df4019790ef8db
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 33a03efd7a clk: rockchip: rk3128: support pclk_wdt get rate 
Change-Id: Ie5dbfe5bd3fdd7868a5db64b96471a5524bde462
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 68d8964cb4 clk: rockchip: rk1808: support pclk_wdt get rate 
Change-Id: Ib204b4c014c3b4cbd35d1f335378b0b399689303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 8afd7ff1e3 clk: rockchip: px30: support pclk_wdt get rate 
Change-Id: I1d58d032c6f3843df3fdee65b1ee9cd3614435b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang a4e491228b clk: rockchip: rk3368: support pclk_wdt get rate 
Change-Id: I8253532cfa6a1d492d68b0e778f625621cad5dab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 981ee0bd7d clk: rockchip: rk3399: support pclk_wdt get rate 
Change-Id: I8634beb815d5129534c36861c2f02e62669889e9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
David Wu 200683ea3d clk: rockchip: Add mac clock support for rk3308 
Change-Id: I972e2b7977f0f94164c72ae2205ec51780eb7373
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2019-04-09 11:09:22 +08:00
Elaine Zhang 5561190119 clk: rockchip: rk3288: add clk_set_default 
support aclk_vio\hclk_vio clk setting.

Change-Id: Ie826c770670598161f22208f504d8762b8597811
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-02-01 16:17:34 +08:00
Elaine Zhang 524f26463d clk: rockchip: rk3066: print arm enter and init rate 
Change-Id: Iaf4ffbb61830b7bb7cef31843f0e9b75c34d08ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-25 16:19:57 +08:00
Elaine Zhang 441bfb788a clk: rockchip: rk3188: print arm enter and init rate 
Change-Id: I604c18050e8ccbbc9aa25ecd8f4379a877239d49
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-25 16:19:57 +08:00
Jason Zhu 14262c55f8 clk: rockchip: rk3328: add case SCLK_EMMC_SAMPLE 
Change-Id: Id2769eefc1692422110152e6dbec7afeb4488c8c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2019-01-25 15:45:08 +08:00
Elaine Zhang 92c6b64268 clk: rockchip: rk3128: print arm enter and init rate 
Change-Id: I0be1752522a83a2d111870e5a8ac95f92bd7f9a5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:55 +08:00
Elaine Zhang 3a1c76d931 clk: rockchip: rk3036: print arm enter and init rate 
Change-Id: Ic9212c8a0f1d50006f7121957b8bd5f34d2622d9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang ec0307ef3a clk: rockchip: rk3288: print arm enter and init rate 
Change-Id: I5a6d564a973111841df6b53a4df64a54f728e116
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 2401c256ec clk: rockchip: rk322x: print arm enter and init rate 
Change-Id: Iab7034c8cef09908a99b5a1e396f6e015da350fb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 093fdd9f5d clk: rockchip: rk3308: print arm enter and init rate 
Change-Id: I6df66d7b5dda643dba49ee87c2a2c0544ddbcded
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang f7913bc128 clk: rockchip: rk3328: print arm enter and init rate 
Change-Id: I80ebeee0d6d8b151061d0bbb0d1d12070dcc6f98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang ae79bf6827 clk: rockchip: rk3368: print arm enter and init rate 
Change-Id: Ib201cf442ce7398bbe8009ce9b7de9dc1f53c587
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 044bc79de9 clk: rockchip: rk3399: print arm enter and init rate 
Change-Id: Ib5e3e0f9a3e1a5b535ec852e7c58966dc0db77cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Elaine Zhang dfce009693 clk: rockchip: px30: print arm enter and init rate 
Change-Id: I0d2a1c6bb92397210314322fd147c4a8a6e81abd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Elaine Zhang ed6f5d94b5 clk: rockchip: rk1808: print arm enter and init rate 
Change-Id: I14f0b0c95b1367266fe9c64050a602ad58208d53
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Jon Lin 8094aeb8cd clk: rockchip: rv1108: add NANDC and SFC clk init 
Currently RV1108 run in 1.2G GPLL.
NANDC need 1200 / 8 div = 150MHz.
SFC need 1200 / 12 div = 100MHz.

Change-Id: Ia3f401b0cf13587209d0d68d76a9891dd3bcf990
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2019-01-22 17:06:35 +08:00
Elaine Zhang 2e8ea5b0f6 clk: rockchip: rk3288: support crypto clk setting 
Change-Id: I066ec163d959b95d0928e07716e3370715aa9898
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-21 09:11:01 +08:00
Elaine Zhang fda8d87331 clk: rockchip: px30: modify the dclk divider to even 
When DCLK use CPLL alone, the DCLK timing is critical value.
The odd-divider spacing ratio is not 50%,
it will affect the setup time of the display.
Therefore, it is suggested that we use even-divider
to make the spacing ratio is 50%.

Change-Id: I07c0fd57dd1f27984f8186f1d7c2f96df2ea10a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-16 16:44:59 +08:00
Elaine Zhang e9dcade2a7 clk: rockchip: rk322x: add clk_set_defaults for clk init 
Change-Id: Ie2bcdf77bb7cdeb9c27b482ce70e4af35fbdc8c6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-14 11:46:32 +08:00
YouMin Chen 51c830f2d2 rockchip: clk: rk3399: support 50MHz and 400MHz for ddr clock 
Change-Id: I9d3a64ce38986f2c48e1f2614bcc274340674aa7
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2018-12-29 09:37:45 +08:00
Wyon Bi 152682ed57 clk: rockchip: px30: support setting clk_i2s_out_mclk to 12MHz 
Change-Id: I53fb5ceac0c423dd90c493d6f05069569c839f4e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2018-12-26 18:45:36 +08:00
Elaine Zhang 8b75ff3444 clk: rockchip: rk3399: support clk dump 
add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang cf04b7e8f2 clk: rockchip: rk3328: support crypto clk setting 
Change-Id: I9e4d58050b087c3da6649efe4d3115da2ce6dce7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang a7c5f87313 clk: rockchip: rk322x: support crypto clk setting 
Change-Id: Id92acae9424fd0b200f9b4f33982f753f6123207
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 51d1c6b1dd clk: rockchip: px30: support crypto clk setting 
Change-Id: I9971fb2b6a40640d78fb259c72aac32582f8e90d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 0cde592567 clk: rockchip: rk3308: support crypto clk setting 
Change-Id: I58967fe70fbae6630fe0404414daaee6b1498b72
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 187d951b8f clk: rockchip: rk3399: support crypto clk setting 
Change-Id: I12cbaeac250f21d4cb05d8ef3ef0e9238cb3f911
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Nickey Yang 0fd8dec7ce clk: rockchip: rk3288: adjust gpll init_cfg 
This patch adjust gpll init nr/no/nf/bw values.
keep them the same as kernel RK3066_PLL_RATE_NB(594000000, 2, 198, 4, 1)
for better clock jitter when hdmi SI test.

Change-Id: I781205d860945214f3f0957882223b8846c00773
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
 2018-12-13 17:35:26 +08:00
vicent.chi 98ebaf0e5b CRU: rv1108 add emmc clk get and set 
Change-Id: I8cbfda46d2f7e84f11dbcca844d00c87559d0aa0
Signed-off-by: vicent.chi <vicent.chi@rock-chips.com>
 2018-12-01 11:40:42 +08:00
Finley Xiao 21ab40a873 rockchip: clk: rk3308: Add flag for clk_set_defaults 
Change-Id: Ic9009b35e395cfe8c2a8f8d367b75b85294c7354
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-11-29 20:40:09 +08:00
Joseph Chen e04b9c6bbd clk: rockchip: rk3308: add arm clk 408M support 
Change-Id: I133576889860c7bae3f722dcd53df6a50c500c35
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-11-29 20:40:09 +08:00
Joseph Chen c111479f4f clk: rockchip: px30: support arm clk 408M 
Change-Id: I98cd856c99ebf2cd77d1a8ff94d2e0a40f0a4bfb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-11-28 16:19:30 +08:00
Elaine Zhang dcb7870427 clk: rockchip: rk322x: fix up the vop clk setting assert error 
Change-Id: Ied72bcb5e92e300eeccd7bfd32285d2eeb4d4860
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-11-16 14:42:28 +08:00
Dingqiang Lin a2795c339d clk: rockchip: rk312x: add sfc clk init 
Change-Id: I5edf0a4b650a57a48f837fa3e007cfaf6a733f92
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>
 2018-11-14 14:32:24 +08:00
Kever Yang 0598134af8 rockchip: rk322x: fix clock assert value 
The value after '<' should be max value instead of 'max-1'

Change-Id: I7a1deaa75b8a931631a54e8dfd154c266251c7fc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2018-11-08 11:03:10 +08:00
Elaine Zhang 823ecf52e2 clk: rockchip: rk3328: add clk_set_defaults for cru node 
Change-Id: I715dde89f691fd95487db53569cc6d8164dc5f28
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-11-02 09:58:36 +08:00
Kever Yang c93db2f356 rockchip: rk3229: tpl skip rkclk_init 
The new rkclk_init is too complecate and not able to run in TPL,
skip it in TPL.

Change-Id: I46f30613050a86ee74060e713283bcb7980c3348
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2018-11-01 08:40:56 +08:00
Elaine Zhang 5a616fcf52 clk: rockchip: rk3288: support aclk_vop freq setting 
Change-Id: Ifb595f244608378bff1e6443dfc017418f28ce2a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-30 09:09:13 +08:00
Elaine Zhang 6259b22e60 clk: rockchip: rk1808: add pll 100M config parameters 
PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6,
postdiv2=6, vco= 3.6G, is best for pcie.

Change-Id: Ie9fddbb32baa0d4b8883b399b0e903b83afc820f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-25 14:03:47 +08:00
Elaine Zhang ed2a409163 clk: rockchip: rk3288: fix up the dclk_vop setting freq error 
fix the commit b328c914c:
(clk: rockchip: rk3288: fix up the dclk_vop freq setting)

Change-Id: Ic4df8bcd4410dbc0484c1ea50d73e70aa64556bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-22 18:03:06 +08:00
Elaine Zhang fab096102c clk: rockchip: rk1808: Support dclk_voplite to set any of the frequencies 
Change-Id: I7ac53f75244388e7fb448a721e55b6b1e789d4d7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-22 09:26:11 +08:00
Elaine Zhang b328c914c0 clk: rockchip: rk3288: fix up the dclk_vop freq setting 
Change-Id: I960a02cba63076afbc845e5ccdfb9f85a553d38b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-19 15:30:55 +08:00
Elaine Zhang ba5feded0a clk: rockchip: rk312x: add cpll freq init 
Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.

Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-19 15:29:24 +08:00
Elaine Zhang 1ae6d6e5c8 clk: rockchip: rk1808: fix up the dclk_raw/lite set rate error 
Change-Id: I0b8c7d0e15501c7ecc3c5acb0e0844e722ad18ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-10 11:27:30 +08:00
Elaine Zhang dad1489559 clk: rockchip: rk1808: support pclk_pmu freq setting 
set pclk_pmu freq before ppll freq setting.

Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-07 09:08:17 +08:00
Elaine Zhang aa8c298733 clk: rockchip: mmc: add mmc set and get phase 
add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-09-29 10:20:11 +08:00
Elaine Zhang cb3c37fcc0 clk: rockchip: support clk_tsadc setting freq 
Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-09-27 18:24:57 +08:00
Sugar Zhang 95f2641240 clk: rockchip: px30: add support clock for SCLK_I2S1 
Change-Id: Iaaacd6fdabe2c702202ffe09dc95cd6d648597d6
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2018-09-25 19:32:33 +08:00
Joseph Chen f680c019e6 clk: rockchip: add debug info for waiting pll 
On FPGA, PLL is fake and can't give a lock state which causes
dead waiting, so that adding a debug message to easily notice
this situation.

Change-Id: Ic7dccedb3d7e5c7588da85bb4c4552b924f60e43
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-09-12 15:51:10 +08:00
Elaine Zhang 45a3782ab4 rockchip: clk: rk1808: add clk driver for rk1808 
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.

Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-08-29 15:25:55 +08:00
Elaine Zhang 41c0dd9b25 clk: rockchip: rk3399: Improve the aclk_perilp0 frequency 
Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.

Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-08-28 19:16:42 +08:00
Kever Yang 47b085748c rockchip: clk: rk3399: fix assert error 
We can not meet the assert condition after we update the code,
fix it so that we can enable the DEBUG option.

Change-Id: I4b3e6b30aae4480ed208f30610493a7d297e90ee
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2018-08-23 11:57:57 +08:00
Finley Xiao a737bf22c0 rockchip: clk: pll: Fix pll rate overflow calculation on 32-bit 
Change-Id: Ide0a10a19218443fa016ee91b5a18cfbf3e0948d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-08-17 10:52:21 +08:00
Finley Xiao 45484bdc51 rockchip: clk: px30: Add support to initialize npll rate 
Change-Id: If98ed54ad785a40efae7da78c5f0122158a3de61
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-08-16 10:19:09 +08:00