Some platform with new GPIO IP implements the low/high
registers with write mask. This configure handles it.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I855357d29e7fba072b867c06a31a049462ebf6ff
This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.
The framework support gic interrupt and gpio interrupt, relative APIs
are provided in: ./include/irq-platform.h
If you'd like to add a new platform support into interrupt framework,
please follow the steps:
1. add relative definitions in the file like other platforms:
./include/irq-platform.h
2. add GICD, GICC and GICR(for GICV3) base address definitions in the
rkxxx-common.h, they are needed in: arch/arm/cpu/armv8/start.S;
3. enable CONFIG_GICV2 or CONFIG_GICV3.
Notice:
1. the framework is initialize in function 'interrupt_init()' of
_sequence_r[]. So you should not request irqs too early.
2. IRQ stack size is configured by CONFIG_IRQ_STACK_SIZE, the default
value is 8KB when CONFIG_IRQ_STACK_SIZE is absent.
Change-Id: I3d9e29873c9d64cd28aabd13a61111438c5902b0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Joseph Chen