CONFIG_OF_LIVE is always available in SPL and U-Boot.
Use CONFIG_IS_ENABLED(OF_LIVE) to unwind as CONFIG_OF_LIVE
in U-Boot and CONFIG_SPL_OF_LIVE in SPL.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I980579d54850ca7655b464688ba9e6bd35f24250
Keep rv1126 support in pinctrl-rockchip.c with legency
Change-Id: I50791c3c30e6efa58d324eaef7bfc4d4aa9e440c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Put the nr_pins information to pinctrl info structure, instead of
calculating in probe.
Change-Id: I3af11d99ef4b0e30c306ebd99a2233cd0c6b97b5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 79d16e45409f928c952b6935d695cd08f9db76b3)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I41ede5737258292e27492e391cf9a981210e4a71
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 623aca88308b4f917f0465cd5dd1514ee781bee8)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Idcbb3fdf4311567c599686d52926a057d1101b6b
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 69a38f81bb55893a8555c899319305c539226a0a)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie8f94cf1a0b33a24bb32d3de8231b7f2db51ddff
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ib0de627d3aee1759965d64852bcd287785538dc0
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 956362c84b0422ea99da947feca2878193c26ade)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I409107119d557b953c904b53e657685907879a3a
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 625ab11fdae3daf346647aaba59abee804e34589)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I07caae48cd4699aa7bbddf2edf7de6863c0a58c2
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I7aaaf9642ee7bed6a2e9f6538a053bd6e1810dd7
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 54e75702c48a9757e82cbe71176c0b5ddcf6a092)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ifdfce706e9b1cbe94300d2bed91182033f23f301
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8541beb86daf3ce7e4be9ca67859aab3dd0daefb)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I9f621c3714260165bab0111e486a1d60ecf33c11
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id7522a4fdd21d42d46c42e6f66b93985064fd9ab
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibf0ba2d879904a06a2fb6722f5886a39c010a7f7
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0)
1. fix with error handle with pin with IOMUX_UNROUTED.
2. add get pin count operation
3. modify drivers/pinctrl/rockchip/Makefile
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1a398c865eb9e9afc38c6aca5431b6546e7260a6
The rockchip_pin_ctrl struct is BSS data, only memset oncetime, but the
driver maybe probed several times, the nr_pins member of struct won't
to start from 0. that will cause pinctrl driver error.
Change-Id: I3d081da8bb91573126c6ee5af345ed73c85bb7af
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Accroding to the datasheet, the pin of gpio3b4 needs to be
recalculated for iomux selecting.
Change-Id: I827be9a51851ee9323a133d8bded8b09e068f1b4
Signed-off-by: David Wu <david.wu@rock-chips.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I6c0f7e50e8b571106627f25ddac008a62bd2994e
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The usage of slew rate is needed to config it at DTS,
such as:
fast speed: slew-rate = <1>;
slew speed: slew-rate = <0>;
Change-Id: I60ea4ddd37ca70adf1dbd504ba1c3c348e41348b
Signed-off-by: David Wu <david.wu@rock-chips.com>
Where need to clean the special mask for rockchip_perpin_drv_list
and rockchip_pull_list.
Change-Id: I98bac7768aa0570c12c947913ef2ea91ae303f95
Signed-off-by: David.Wu <david.wu@rock-chips.com>
Change-Id: Ibf85312e909e040ef0efb120efe3f48c4a2c6ab9
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Using the name IOMUX_UNMASKED of flag is not so suitable, pickup the
IOMUX_WRITABLE_32BIT name. And need to clean the value when set the
iomux.
Change-Id: I3e2d69702f4669770ff933ba2c40a641a924b55e
Signed-off-by: David Wu <david.wu@rock-chips.com>
There are no masked bits for pmu_gpio0 iomux, so add the IOMUX_UNMASKED
to read iomux register at first, it would not change others' bits.
Change-Id: I5a0cf5f15c90fa769c3447d4e5f5380630b10c3b
Signed-off-by: David Wu <david.wu@rock-chips.com>
The most pins of rk3308 are 2bits iomux, but the banks's register
width is 0x8.
Change-Id: Iaf79232a552a5e239610bce533fe884df4a4743c
Signed-off-by: David Wu <david.wu@rock-chips.com>
Some case like rk3328 gmac rgmii pins has 22 pins, so
need to change the max pin entry to 30, otherwise it
make something not work.
Change-Id: I6897ce6ff995713da75c2094d857b3eb95b77204
Signed-off-by: David Wu <david.wu@rock-chips.com>
Use live dt interface for pinctrl_select_state_full()
Change-Id: I1cc892f59004a48f4f2e6adac2a17a03dbfcb81c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Uart2 and uart3 both have routed bit, use their rx pin to
switch m0 or m1.
Change-Id: Iae64bb675a1f8cc8e54c7b798bffcf89d68fb64f
Signed-off-by: David Wu <david.wu@rock-chips.com>
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.
Change-Id: Ie419b40664215b4b23a97138398102745f9875e6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Use this drive to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Change-Id: I86b5f25feb13c92a56103aef292a492e8f2accc8
Signed-off-by: David Wu <david.wu@rock-chips.com>
David Wu
Joseph Chen
Jianqun Xu
Jason Zhu
Masahiro Yamada
Kever Yang