CONFIG_OF_LIVE is always available in SPL and U-Boot.
Use CONFIG_IS_ENABLED(OF_LIVE) to unwind as CONFIG_OF_LIVE
in U-Boot and CONFIG_SPL_OF_LIVE in SPL.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I980579d54850ca7655b464688ba9e6bd35f24250
Keep rv1126 support in pinctrl-rockchip.c with legency
Change-Id: I50791c3c30e6efa58d324eaef7bfc4d4aa9e440c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Put the nr_pins information to pinctrl info structure, instead of
calculating in probe.
Change-Id: I3af11d99ef4b0e30c306ebd99a2233cd0c6b97b5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 79d16e45409f928c952b6935d695cd08f9db76b3)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I41ede5737258292e27492e391cf9a981210e4a71
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 623aca88308b4f917f0465cd5dd1514ee781bee8)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Idcbb3fdf4311567c599686d52926a057d1101b6b
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 69a38f81bb55893a8555c899319305c539226a0a)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie8f94cf1a0b33a24bb32d3de8231b7f2db51ddff
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ib0de627d3aee1759965d64852bcd287785538dc0
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 956362c84b0422ea99da947feca2878193c26ade)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I409107119d557b953c904b53e657685907879a3a
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 625ab11fdae3daf346647aaba59abee804e34589)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I07caae48cd4699aa7bbddf2edf7de6863c0a58c2
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I7aaaf9642ee7bed6a2e9f6538a053bd6e1810dd7
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 54e75702c48a9757e82cbe71176c0b5ddcf6a092)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ifdfce706e9b1cbe94300d2bed91182033f23f301
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8541beb86daf3ce7e4be9ca67859aab3dd0daefb)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I9f621c3714260165bab0111e486a1d60ecf33c11
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id7522a4fdd21d42d46c42e6f66b93985064fd9ab
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibf0ba2d879904a06a2fb6722f5886a39c010a7f7
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0)
1. fix with error handle with pin with IOMUX_UNROUTED.
2. add get pin count operation
3. modify drivers/pinctrl/rockchip/Makefile
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1a398c865eb9e9afc38c6aca5431b6546e7260a6
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.
Change-Id: Ie419b40664215b4b23a97138398102745f9875e6
Signed-off-by: David Wu <david.wu@rock-chips.com>
The RK3399 has a total of 9 I2C controllers. To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.
For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.
Change-Id: I7ad9400f05d3ee89263ecd2bcc391483934b6c74
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8c2bb589e29d5cb89e10c3ddd23b28d949fa9693)
Apparently, our earlier assumption that the BROM will always set up
the iomux for SDcard communication does not always hold true: when
booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard
pins are not set up and need to be configured by the pinctrl driver to
allow SD card access.
This change implements support for setting up the SDMMC pins in
pinctrl for the RK3368.
Change-Id: I41d4ccc546e5256713edc162bb7e3ec622843c16
Reported-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit fd0a1ba52ec65e82caf163d0074e768c3abc57ae)
Update the pinctrl driver for the RK3368 to support a live device tree.
Change-Id: Iba0c742549755a1a9d9edb7697faeb10b4edb247
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d2edb968c4dbd116aaddf994ec540eb4ef4d9cee)
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), if we use dev_read_u32_array(), the interface
will use the ofnode directly and end with:
assert(ofnode_valid(node));
Use fdtdec_get_int_array() instead.
Change-Id: I1fc90ad0bd22451856e97be7728ba9996bf3bc0c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Fix the IOMUX setting for SDcard CMD pin at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dts from kernel is using rk3228-pinctrl as compatible name,
need to sync with it to make the driver work.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).
This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.
This adds pinctrl support for the MMC controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* configures the RGMII pins
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines. As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Currently, drive-strenght to 12ma are described and supposed to be used
on RK3288. However, the pinctrl driver for this SoC only handles muxing
and pull up/pull down via PU/PD control registers. So complex IPs like
GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.
This commit adds support for handling drive-strength of 12ma, when it's
defined in the DT.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This reverts TXCLK toggling that was accidently dropped while reworking
commit 2454b719fb ("rockchip: rk3288: Add pinctrl support for the gmac
ethernet interface"). So the TX clock is enabled and we can use
GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled
(!PINTRL_FULL).
Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
We should not handle this pin explicitly from pinctrl. GMAC driver takes
care of it by using a "reset-gpio" in the DT.
This commit removes pull up for GPIO4B0.
Fixes: 2454b719fb ("rockchip: rk3288: Add pinctrl support for the...")
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add support for the gmac ethernet interface to pinctrl. This hardcodes
the setup to match that of the firefly and Radxa Rock2 boards, using the
RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
SDMMC-PWREN is a pin to control voltage for SDMMC IO, it may
be high active or low active, the dwmmc driver always assume
the sdmmc-pwren as high active.
Kernel treat this pin as fixed regulator instead of a pin from
controller, and then it can set in dts file upon board schematic,
that's a good solution, we can also do this in u-boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This change covers the pinctrl drivers for the Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.
We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move GRF register bit definition into GRF header file, remove
'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
definition in grf header file and pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add driver to support iomux setup for the most commonly
used peripherals on rk3368.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
David Wu
Joseph Chen
Jianqun Xu
Kever Yang
Philipp Tomsich
Paweł Jarosz
Romain Perier
Sjoerd Simons
Andy Yan