This reverts commit d77dbb6e1c.
Reason: if we remove TPL code, there will be different compile
path for SPL to initial platform, which takes some unknonw issue
in kernel. So let's bring back TPL.
Change-Id: Iee1ab45d0a622425b616b22f8fbcdb7b28f057f7
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This patch auto detect BW16 constitute by byte0 and byte2 or
byte0 and byte3.
Change-Id: I22a8fa70db1d996573004320196c0892d5380f64
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
after system test, 32bit interface use pageclose can improve
performance, 16bit interface not improve.
Change-Id: Iecac7aae1e5f8ec4f162200d80be16f1b91180f5
Signed-off-by: CanYang He <hcy@rock-chips.com>
Use CONFIG_SPL_KERNEL_BOOT for thunder boot to stay the same with SPL.
Change-Id: I0d2f0a91a5f628233de1cb848519fd76b692a2af
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
1. set the noc ddrtimingc0.b.wrtomwr for LPDDR4
2. set the noc ddrmode.b.mwrsize for LPDDR4
3. update the noc ddrmode.b.burstsize
4. update the controller timing for 328MHz
5. set ddr4timing to 0 except LPDDR4
6. calculate ddr4timing using *_L timing for DDR4
Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fb
Signed-off-by: YouMin Chen <cym@rock-chips.com>
lpddr4 reg0x107/108 is for clk driver strength.
for other type of dram this register is for A6/A8 driver strength.
Change-Id: Ia0acbe03574ad5a1a4ecdaa2c0f53cb9a45c034b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Enable it by set CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT to y.
Change-Id: I54db1d1b33fc9e063c05bc4aca85589b495a4db9
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Modify ddr support frequency to match PLL setting.
Change-Id: I1d93b2178933ada04e178bd068a8fec4ef43a4de
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Use CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE to select dram type.
Use the same define with arch/arm/include/asm/arch-rockchip/sdram.h (0 for
DDR4, 2 for DDR2, 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4).
Change-Id: I982db49c1881f6975afd4ba48f88ee3dd9286d3e
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
If CONFIG_ROCKCHIP_THUNDER_BOOT=y, it will enable ddr fast boot.
Change-Id: Ia43039dd1247ebb937aaa8b6d9a9103df2dfe1f5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Remove the config about SDRAM_COMMON_CAP_DETECT,SDRAM_COMMON_OSREG,
SDRAM_COMMON_MSCH_RK3399 and SDRAM_COMMON_MSCH_PX30.
Change-Id: I17f2bdae585454a1d869ae9d967843d1d169381f
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Both px30 and px30mini are using ddr3, change the default
dram type to ddr3 to adapt it.
Change-Id: I177dc41cd2a5e6a1cac718c75fa5a2541050ee6d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
evb-px5 has only 1 CS, update for it.
Change-Id: I5393d21c88d44457a590cb31df31eb59d20bbf02
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
Change-Id: Iadcf7065f02ee779d3eeee1cb70fd3e9905e1b3f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
use rockchip_setup_ddr_param to setup ddr parameter.
The dram_init() and dram_init_banksize() make use of
sdram common code.
Change-Id: Icfc6cbef9fcc128e3a835184b46b89b9b22aab16
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Tang Yun ping
Zhihuan He
Joseph Chen
YouMin Chen
CanYang He
Kever Yang