In general we should avoid calling malloc() and free() repeatedly in
U-Boot lest we turn it into tianocore. In SPL this can make SPI flash
unusable since free() is often a nop and allocation space is limited.
In any case, these seems no need for malloc() since the number of bytes
is very small, perhaps less than 8.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d13f5b254a (spi: Extend the core to ease integration of SPI
memory controllers)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ca2abb75a086d8b0bdb51689f331ba8f1a146379)
Change-Id: Ia76abf7491780b1984eb81c6c78796bcc0141095
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 567a3eb7956f98af4ed065499898c6d0ac6443c7)
Change-Id: Ie9fdf0cbee364fc33965e3234d7457702bd0120f
Spetial patch for GD devices cause u-boot SPI Nand MTD bad
supporting for GD, and the u-boot mainline haven't synchronize
with Linux.
reference to following Linux commit:
commit f1541773af49ecd1edae29c8ac0775253a0b0760
Author: Chuanhong Guo <gch981213@gmail.com>
Date: Sat Feb 8 15:43:50 2020 +0800
mtd: spinand: rework detect procedure for different READ_ID operation
Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
Change-Id: If60d0281eb963486639d5b4ce1939ad2b219c8d6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.update interface to get register base
2.update interface to scan subnote
Change-Id: I14b9f582219b775d8c94ea38ab4bb0527d05c37d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This converts the following to Kconfig:
CONFIG_SPI
This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver. For now, just update
the CONFIG tests. This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
(cherry picked from commit f1b1f77060beadbfe9f42a3be00019bd025afbd6)
Change-Id: Ie9f15ada869105eb407f41d4df7eecbaa916b940
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.
Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Change-Id: I741ce99a6b6cf57c248426549c0047d636d9e43e
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9b14ac5cc2294ac3eaae92421abff27ed3e6caae)
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.
Change-Id: Idc0280488ce052492579ee8e52f6084aa0840f3b
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ea5512eb095067dda27930246792d2957feb9434)
Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.
Change-Id: I0d004adc09e2fb32e88b17b0f060aecc0b7bda35
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9573db654d1999a1dfde6469782aa8d7cf3d589f)
Waiting for SPBDCR == 1 is not required and is covered by the
subsequent wait for SPSR_SPRFF, so drop this.
Change-Id: Ie943ac6feff57e478a7b2e7325eac9b5438c0374
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 118226495249268a35e604b2e6309801699f6224)
Just replace unsigned {char,short,long} with u{8,16,32},
no functional change.
Change-Id: Ie9a9d331acb364d9b27a72a052a511a8da61c471
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0e6fa20b14ed27ef667ddb31c8e7c620417ee4f5)
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Change-Id: I8b936d2862a1ef4bc2451d54a1808b7b49710b17
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fbebea27e16eb760f1f2109a7535003bf359ba2b)
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 7b0947787358c6b277431d6b76ce043d8bec641d.
Change-Id: I9953c2529a611950db1de168d772607329f827b7
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e80fa2c2c0870f7c17e233ecc07552e1082c1513)
As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 37434db29be495ef41f204a97b8bf13b1418f97d.
Change-Id: I91af9f7fc85430b3c0c9c095f097e6692cac91ea
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5270df2836761909864d9b548bf4b7f7f3a51484)
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm
Change-Id: I37b02101bd88b607f0f9eca79fdbb7cc1e85ed4d
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 18f8d4c60d26e6cd113461c5d716c64897c3f112)
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
(cherry picked from commit ee1e600c13d16febd517ab7d0d2c243db174789b)
Change-Id: I564708bb6517b699749e8a54c013d032f785e459
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
ATMEL_SPI is now fully converted to driver-model and
respective boards switch to DM_SPI as well,
so make default y for ARCH_AT91
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
(cherry picked from commit 89d4fc153bb5c3830ab9e75e1690738cccea0322)
Change-Id: I3c3da47c05f7fef7a2129c5325c4ddf7b596b2cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Change-Id: Ia43a1c2dc2fc7e02a7d5613c8aac31c63bd0c37c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 37434db29be495ef41f204a97b8bf13b1418f97d)
All board configs are now enabled DM_SPI for SPL and
U-Boot proper, so now its time to drop non-dm code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
(cherry picked from commit 7b0947787358c6b277431d6b76ce043d8bec641d)
Change-Id: Ifa87682ea641368d73be6a059c00d194a668bf4b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.
Change-Id: I12cb7f90bd11ca5687da7992382fb3b447d5ec1c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9bf48e2ee8a0174adfb0f18d110198e4ca042284)
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Change-Id: Icfcb73b19f630bda5faf2d8bbb03efff6db9c933
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 63018a3eddd5d9c64f7ee42615a63c6a67ab484d)
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Change-Id: I3e52a45a49f96177d1c0d3781d8d98d7df5d9e0c
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4b5f6c52e78d43710a0d062e31de741ec76ceea1)
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Change-Id: Ifecfe693bdc9316da7d23db43f8764885e3cb786
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit bcdcb3e61ebd0550355883aed3978028d0e7778b)
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Change-Id: I2654951199094c51609c5402b5abd62438bbf1dd
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d3d8aaec7401703079f296a6460fe649fb06581b)
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Change-Id: I876d86fbf05feccebf6ded5f3acfa09a6cd15ea2
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fc282c7bcb6a622ce1a0cf82c55654dec5bcb0cd)
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Change-Id: I13be86b6b7da544ff64656fdb62ea79d5ee16d26
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c6b4f031d96a4e1d59761b294829b058b098f3df)
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
struct udevice *bus = dev->parent;
Change-Id: I6413fbdc32b1365d545033382c40fa39f85e5b84
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b2b41d27775823b8e19f6816aa08ffca0e234ade)
set_mode, set_seed functions has separate function pointers
in dm_spi_ops, so use them in relevent one instead of
calling from claim_bus.
Change-Id: Ifbe121f3a84c8b2ce007fe5a80fdd213b9f78a82
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 84807922874e03895bbf15c4472a2dcee8fbbd03)
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig
already enabled DM_SPI, so non-dm code make no use
of it hence droped.
Change-Id: I6864c71a8e9a97619fbe1989856077285aa2408e
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 15927aef02b7e7b5921bd1470ce145c2fa03ef08)
Change-Id: Ia9f6139d87f28ef8bbab5effb15b3e00e53e732d
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fbca0e66cc982325d8031094736d79ed007e42e2)
Change-Id: I70b43d668f905f236e18493c07ac6c369b7ca2d1
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4a942f49b891872727aa0bdba58e2ca513fc455c)
Change-Id: Ib34e1271ed6dd812bfb21bc2162b30d27b014498
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2c4b096b4c3e9d115b43edb23b1592a297076ae4)
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
(cherry picked from commit bbdf38698ee5c96138868d563c6825cd48bb26dc
Change-Id: I6c99c0696716c148a9f8a3255111b23749c78a6b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: Id2769d0405f96348de67cdd24df8a82a35101637
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7b819b569e92fd9b9b1baf160cd946a523fde1ce)
Change-Id: I51b0a222d7f5d4bf8925f7544c50d8f35da235e2
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a5dfabea19f961826509118513f833cea25797bb)
Change-Id: I66c533e5c556c26b771037bc7eee5ceff01f5cb9
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 95d3877a5818cc3f149a9d443637ff145bbaaabb)
Check if ns before and not after dereferencing it.
Indicated by cppcheck.
Change-Id: Ic9a2491051754fef64ce7ad4a9a5377fc3aad6db
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 923837e159c5886be38c7a83a2d6bc489b35c1f4)
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.
Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)
Reviewed-by: Marek Vasut <marex@denx.de>
Change-Id: Iee14939326b5512a7704ccbcfd9795d1a1f6aa3b
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 58c125b9e2b232ce73ed7b24ba7b1ca5ff41c5bd)
Jason Zhu
Jon Lin
Simon Glass
Bernhard Messerklinger
Yifeng Zhao
Adam Ford
Eugeniy Paltsev
Marek Vasut
Tom Rini
Christophe Leroy
Jagan Teki
Sjoerd Simons
Tuomas Tynkkynen
Heinrich Schuchardt