these flags will be used by other output interface, so remove
DSI special assign.
Change-Id: Ieb3a20e62c2b899e6757635eced86b85e1fb22f7
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This patch adds support for Analogix eDP TX IP used on RK3568 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba4e5fd15a35bdbaf373
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic60d8bb86a53f686e8c46323b58d099c727a36d3
The phy framework is only allowing to configure the power state of thePHY
using the init and power_on hooks, and their power_off and exit
counterparts.
While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.
That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).
So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.
phy_configure will actually apply that configuration in the phy itself.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Icd170eaef9a1dbe21e0c7664b797a27877c703b5
It is possible that users of generic_phy_*() APIs may pass a valid
struct phy pointer but phy->dev can be NULL, leading to NULL pointer
deference in phy_dev_ops().
So call generic_phy_valid() to verify that phy and phy->dev are both
valid.
Change-Id: I0d19180ae8524eb240f4afd6ea55d5d0f2907798
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 64b69f8c89352975c25730bcca4bf8af2296297f)
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.
Change-Id: I11c95af8c1b54f2dad41891f6d0edb8d9fac6606
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 4e1842988364446ba0cf2171d1eebb53c15bc44e)
If sink is hdmi, but not set to hdmi mode,
will cause no sound after entering Android.
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I5a8cc308c8064e0c372162145b1e814765e80630
This reverts commit d77dbb6e1c.
Reason: if we remove TPL code, there will be different compile
path for SPL to initial platform, which takes some unknonw issue
in kernel. So let's bring back TPL.
Change-Id: Iee1ab45d0a622425b616b22f8fbcdb7b28f057f7
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Otherwise the time is still working in kernel if there is no
one to update it, which always wakeups system suspend.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic2291b26730557c50fb8cbd505d05b40bb582c74
1.erasesize_shift, erasesize_mask
2.it's useful for mtd_blk.c
Change-Id: I0bd184fc86637849fbd079f9f539387465a07b8f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
We use function spl_rockchip_otp_start & spl_rockchip_otp_stop to
realize the different of each chip's otps, such as mask area and
secure config.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3b5d0377d78e5c2ed6e8ed52a89cadefc4994be1
Reset the clock phase when the frequency is lower than 52MHz.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I49c50779ab5e1103d815cd2be1a7c9603cea397a
CONFIG_OF_LIVE is always available in SPL and U-Boot.
Use CONFIG_IS_ENABLED(OF_LIVE) to unwind as CONFIG_OF_LIVE
in U-Boot and CONFIG_SPL_OF_LIVE in SPL.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I980579d54850ca7655b464688ba9e6bd35f24250
Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5
If there was an i2c transfer error like iomux error,
should clean the ipd status, it might cause kernel i2c
irq error handing.
[ 0.690749] rk3x-i2c fdd40000.i2c: irq in STATE_IDLE, ipd = 0x10
Change-Id: Ia127edada535288e9b984d6dc0dff813e6152eff
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch fixes the following issues for rk3568 usb2 phy.
1. Set utmi opmode to normal mode for rk3568 usb phy when usb
phy enter suspend mode via usb phy grf. It can help to avoid
the DM/DP floating and the line state be detected as 2'b11.
2. Fix the offset of INT_STATUS_CLR. It can help to avoid
triggering the linestate irq constantly.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ic108e116d1473341b61743ec4244bc034a95f501
The i2c5 xfer went wrong because of io-domain was not right
and was configured correctly in uboot to ensure that kernel
was right before initializing the io-domain driver.
Change-Id: Ic2f94952f7a851dc5b781af9f31bba2562b5a2b5
Signed-off-by: David Wu <david.wu@rock-chips.com>
Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.
But from RK3568, we add gpio alias to indicate gpio index
information and index is removed from gpio node name, ie:
gpio@fdd60000, gpio@fe740000, etc.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I56e45941f9572fbc6a5a5916896e12f6eff9dcf3
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.
Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ia33d3de222a6c7f263290f4098d0a5e557a9d568
Algea Cao
Wenping Zhang
David Wu
Joseph Chen
Jon Lin
Guochun Huang
Wyon Bi
Vignesh Raghavendra
Jean-Jacques Hiblot
Elaine Zhang
Jason Zhu
Zhihuan He
Andy Yan
Sandy Huang
Tang Yun ping
Shunqing Chen
Zorro Liu
Yifeng Zhao
Lin Jinhan
Jianqun Xu
Finley Xiao
Ren Jianing
William Wu