Since v2.80a, dwmmc controller introduced the card write threshold for
HS200 & HS400 mode. So CardThrCtl can be supported during write operation, not
only read operation.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I7f345660107c2978d2f874d36f2dffd2acdfbcb6
We set the fifo_depth to 0x100 word in Rockchip platform, and
fifo_depth/2 must be multiple of dma_multiple_transaction_size.
So we can set DWMCI_MSIZE to 6 according to max
dma_multiple_transaction_size being 128.
The DWMCI_MSIZE must be set as larger as possible. If not, dma fifo will
be full, and crc error occur when the clock stop during the data phase.
Change-Id: I013b6f9c272edbc723b2f627e88d30d653c42d1b
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
dw_mmc supports two transfer modes in u-boot: idma and fifo.
This patch adds autodetection of transfer mode and eliminates setting this in host config struct
Change-Id: I0eafb78c3fd171827664e320b8959f3c5e27094a
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This patch enables stride PIO for better burst mode
support on some rockchip platforms, for instance rk3128,
etc. It uses ldm and stm to make multiple accessing from
CPU under some ARM architecture.
Design Note:
1) Carefully test it beyond the armv7(m) core since I don't
test them! If you disassemble the code, dwmci_memcpy_fromio
may be changed to use ldmia.w and stmia.w, as well as some
other optimization for push/pop stack operation, but they
are all fine!
2) Do *NOT* remove noinline and __volatile attributes as
you could fall into trouble by the optimization of GCC.
And please invent new attributes if you use *OTHER* compilers
which have their own keywords claiming the function to be a
"plase don't inline the function and please don't reorder the
groups".
3) If you want to use this feature for other rockchip platforms,
you could append new config in rockchip_dw_mmc.c. But now we only
have CONFIG_ROCKCHIP_RK3128 which means we just enable it for
rk312x platforms.
4) Stride PIO is determined by both of host->stride_pio and
the data payload. The intention of it is to make the block
accessing faster. So now only enable it for who's data payload
is larger(or equal to)than 512 Bytes.
5) MAX_STRIDE means we support burst MAX_STRIDE * 4 Bytes per
stride. Of course you could change that, but please read the
comment before it in the code and do it carefully.
How to test?
1) Prepare a memory, for instance, 0x70000000 on RK3126c.
=> mw 0x70000000 0x55aa55aa 0x200
2) Check it to see if 0x70000000 ~ 0x700000200 are all 0x55aa55aa
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
3) Fetch data of 0x70000000 ~ 0x700000200 and wrrite them to eMMC,
for instance, LBA 0x10000, and blk count is 1 as one blk means 0x200
bytes.
=> mmc write 0x70000000 0x10000 1
MMC write: dev # 0, block # 65536, count 1 ... 1 blocks written: OK
4) Clean the merory buffer and double check it
=> mw 0x70000000 0x0 0x200
=> md 0x70000000 0x200
70000000: 00000000 00000000 00000000 00000000 ................
70000010: 00000000 00000000 00000000 00000000 ................
70000020: 00000000 00000000 00000000 00000000 ................
....
5) Well, now let's read back the data from eMMC from the LBA
we wrote before.
=> mmc read 0x70000000 0x10000 1
MMC read: dev # 0, block # 65536, count 1 ... 1 blocks read: OK
6) We expect the 0x70000000 ~ 0x700000200 should be 0x55aa55aa instead
of 0x0 which is cleared by step 4).
=> md 0x70000000 0x200
70000000: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000010: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000020: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
70000030: 55aa55aa 55aa55aa 55aa55aa 55aa55aa .U.U.U.U.U.U.U.U
....
Great, we see that the write and read eMMC are finished well and
the data payload is correct as expected!
Change-Id: I9b68c335449550b95f1a8f5841d46821346e45af
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
For the HS200/HS400/SDR104, tuning is needed to determine the optimal
sampling point. Actual tuning procedure is provided by specific host
controller driver.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some arguments don't need to pass to dwmci_setup_cfg.
They are already included in dwmci_host structure.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
According to DesignWare TRM, FIFO_COUNT is bit[29:17].
If get the correct fifo_count value, it has to use the FIFO_MASK
as 0x1FFF, not 0x1FF.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Ziyuan Xu <xzy.xu@rock-chips.com>
There are no places to call these functions.
It should be used the callback function.
Then it can be used as static functions.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This e,g is wrong. Maximum/minimum e.g values are swapped each other.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These comments were missed when the original code was written. Add them to
help people port their drivers over.
Signed-off-by: Simon Glass <sjg@chromium.org>
some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Clksel value is exynos specific value.
It removed "clksel_val" into dwmci_host and created the
"dwmci_exynos_priv_data" structure for exynos specific data.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Pavel Machek <pavel@denx.de>
Restore the platdata(property of dt) into host struct.
Then data's information is maintained and reused anywhere.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The way that struct mmc was implemented was a bit of a mess;
configuration and internal state all jumbled up in a single structure.
On top of that the way initialization is done with mmc_register leads
to a lot of duplicated code in drivers.
Typically the initialization got something like this in every driver.
struct mmc *mmc = malloc(sizeof(struct mmc));
memset(mmc, 0, sizeof(struct mmc);
/* fill in fields of mmc struct */
/* store private data pointer */
mmc_register(mmc);
By using the new mmc_create call one just passes an mmc config struct
and an optional private data pointer like this:
struct mmc = mmc_create(&cfg, priv);
All in tree drivers have been updated to the new form, and expect
mmc_register to go away before long.
Changes since v1:
* Use calloc instead of manually calling memset.
* Mark mmc_register as deprecated.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
dw-mmc.c is the general driver file.
So, remove the exynos specific code at dw-mmc.c.
Instead, exynos specific cod can be move into exynos-dw_mmc.c.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
To prevent the confusion, use the get_mmc_clk() instead of mmc_clk().
get_mmc_clk() is more exactly name.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Jason Zhu
Paweł Jarosz
Shawn Lin
Ziyuan Xu
Simon Glass
Jaehoon Chung
huang lin
Marek Vasut
Pantelis Antoniou
Rajeshwari S Shinde
Wolfgang Denk
Amar