This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a1c1605dd46ed31fb7ca15c7c26572739f636ec
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ib60f306cb9e8abec9557e92a6d04d76a7071b9ea
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I214b0b2fbe04a139de911435c4abf224264f5495
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I313674274fc2eddb7717ba76c537cd668d6a492b
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id1d2405397d0c2f59b7bf1e341cdf66b023e4226
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ic845d330465c1bb8f7868fb188e5bf30c865b9b5
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id5ffc944a2c066d78a784aeb28ecb846b53e52fd
For Rockchip, need to obtain the current link speed to
configure the tx clocks, (for example, in rgmii mode,
1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate)
and then enable gmac. So after the adjust_link(), before
the start gamc, this intermediate stage needs to configure
the clock according to the current link speed.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9a46da28abca0544cb0a56b0a0574e2fd1de0c52
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I952ac6cc6a4278c887b530bd6d387752358c89a8
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc60f49f36bb2011454370ed7fcc6d9db3b34d9f
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I428c7158c113143a7e51296705fabde6f05eb0f6
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia1d19c61fb8a2c8540b3dfda53b6aeb3b72acb7f
Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4204948ae6a0408f7d642007d27923a3c6941562
Implement the callbacks to get phy mode interface and txclk
rate configuration.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I0a5265347936c1bc821c175eea1698d2624d4873
Add dwc eqos for imx support.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I49127be057a49e6b45e37f940d523d808c20343b
Update eQoS and fec ethernet drivers to support shared MDIO framework
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf5f3ca585190c6469b68195aaea2499242a0096
For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.
To resolve this problem, introduce an eth phy generic driver and uclass.
After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.
When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice83493e9e1caf3842f9ce0c129e29ad46cc0532
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices. Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8e106f4360aa46289e0ed551f8f685cad9dc6269
The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buffer address to 0, it
is assured the DMA will not use such a buffer and the buffer can be
updated without any interference.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If70a57f195c146d571de20385b55ff75f7dea7db
This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.
By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6271396aad6abac3fb11e5e742a3b2c9e7cc355b
The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.
This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia05e8a43d707088bc3699b7d00434c8d12d2692f
Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7a37f8a1fd51b2b7ca4fb557885d711ebd72c49c
This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.
Fix this by adding the necessary wrap-around.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf0f5dba76c232af1cbef628c099aaf43542757d
The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I5b116fa58de65b3958c3ddd87f6c182c532b9542
Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6ecabcffc4782f1e641d8ee1021f6c3caf360707
Add management of property "reset-gpios" in the node identified by
"phy-handle" to configure any GPIO used to reset the PHY.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia7dfcafc2e2f90a5ca48205dd2562fb62a3d6d84
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc8a780b8a7e1be6f827ca901d0b1f2b384ca627
Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).
To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.
This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c
warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
int board_interface_eth_init(int interface_type, ....
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7301e49ef8e51ecdde0629a69d7bcc07465952d0
This patch solves many warnings when compiling with W=1:
warning: no previous prototype for '....' [-Wmissing-prototypes]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice01d9d56324b450f313a4a74e5039581e20a08e
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ie696f22dd260f6712c61744c60dc9d5a64737a5a
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I53a73274b6386f8a510b590a0f7ce1923f7b5528
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iae1c8e2414b655639c42f7098a097c6a0a1e5792
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):
- network drivers
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
<-- phydev is connected to dev which is UCLASS_ETH device
if (priv->phy_of_handle > 0)
dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
<-- phydev->dev->node is overwritten by phy-handle DT node
- PHY driver in .config() callback
int node = dev_of_offset(dev);
<-- PHY driver uses overwritten dev->node
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "property"))
...
As result, UCLASS_ETH device can't be used any more for DT accessing.
This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I31fcf01cfb19894bc90d198d9138c1fd3e25802e
Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.
Change-Id: I7be6b46fc17aa7f7a3a40677de0c18c9dd095c52
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a8f33034f2ed029dd04aae4cfdf11bf1f13a03a2)
This converts the following to Kconfig:
CONFIG_SPI
This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver. For now, just update
the CONFIG tests. This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
(cherry picked from commit f1b1f77060beadbfe9f42a3be00019bd025afbd6)
Change-Id: Ie9f15ada869105eb407f41d4df7eecbaa916b940
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and
move it into arch/powerpc/include/asm
Change-Id: I37b02101bd88b607f0f9eca79fdbb7cc1e85ed4d
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 18f8d4c60d26e6cd113461c5d716c64897c3f112)
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
(cherry picked from commit ee1e600c13d16febd517ab7d0d2c243db174789b)
Change-Id: I564708bb6517b699749e8a54c013d032f785e459
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I638846de7db29711fb7c778cc8304b507de057fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 48263504c8d501678acaa90c075f3f7cda17c316)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I6c0f7e50e8b571106627f25ddac008a62bd2994e
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We do not need to assign-clock for every driver in Rockchip platform,
only below module need this feature, remove it for boot time optimize:
- GMAC (need set parent from dts)
- CRU ARM clock (rockchip board will call set_armclk_rate() instead)
- VOP (need set parent)
Change-Id: Ie8facfb7499323f4649e0e1d908f850de1338e12
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Change-Id: Iba16013ad469196e0d0674fa62d1dcecf6749968
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3328-specific logic necessary to reuse this driver.
Change-Id: If00fc0dc957cf3e29faa1d1d0611a6e6edd29ced
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Change-Id: Ie669aefd1af254f4f7c71ac82decc01bd61e9e5b
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu
Ye Li
Fugang Duan
Alex Marginean
Marek Vasut
Patrick Delaunay
Christophe Roullier
Carlo Caione
Pankaj Bansal
Grygorii Strashko
Wenbin song
Adam Ford
Christophe Leroy
Jon Lin
Masahiro Yamada
Kever Yang