When the devices without firmware boot from the SD card,
the iomux of the storage interface is not configured,
so the firmware cannot be upgraded to the storage.
It needs to be configured by uboot.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If3f4a0a37e37b2fc9e0f4d7e5869dbf156649505
It's a way to test system stability before kernel stages.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6679fbbbaa7233750b409b6b832849d8dbd36893
The RNG driver is separate from the Crypto driver.
Change-Id: I51b39e337106988d5444246a53e46c27644effb0
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.
With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
(cherry picked from commit 77aace579a9a84c74e99d2e86ecc08b1d9ca402b)
Change-Id: Id289de433e49d396a95e3a72acf210be3a2d910b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This patch set the USB 2.0 PHY0 port0 and PHY1 port0 and
port1 in suspend mode to save power. And set the USB 2.0
PHY0 port0 for OTG interface still in normal mode.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I684e3bf8ce7934402e745ea7cfe110b987f5d9db
The page offset is need point to empty page.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ib677e2937fd39b4b56622066cecfbe9a0da297ce
Since the sdmmc0-det is set to pcfg_pull_none and there is no sd
card, it has a current loss of 2 mA.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ifb6184d134155a39dc6986632a8346ffc342263f
arch/arm/mach-rockchip/fit_misc.c:26:12: error: ‘fit_image_check_uncomp_hash
defined but not used [-Werror=unused-function]
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If959d9e946351ce41dd1374b4c69f182f5273d39
Without this, there is a dead loop path:
hang() => spl_hang_reset() => do_reset() => failed to reset => hang()!
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8553bde97bd45ca63e5a12aca1acfc939301b04f
It's a long story to explain why to set gpio0_c2 to pull down, start
from ...
The rk1808 suspend supports to swith 32k clock source, BUT need the
low level for each source clock.
clk_32k --- ext_32k from pmic for example (pin on SoC is AWK13)
|
--- int_32k divided from 24MHz
The pin AWK13 default to be GPIO0_C2 which is normal state defaultly.
When the software try to switch clk_32k from int_32k to ext_32k, but
the pin is in normal state, unluckly for some board it's high level,
the result is the switch never be done, till device try to do suspend
and into a halt state.
Make the gpio0_c2 to be pull down as default state for kernel.
Change-Id: I6ae5859352d9a680166b4c711e25491a60442209
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Support rollback index when enable CONFIG_SPL_ROCKCHIP_SECURE_OTP.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id865d9b13f92a322b576dd0168805e05acbdbcbf
Set the APLL_HZ to lower frequency in spl when the pmic is not
available.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id540ff174ef93c3d9ea22bb37dc26ca7b587a5b7
Joseph Chen
Yifeng Zhao
Lin Jinhan
Patrick Delaunay
William Wu
Jon Lin
Tang Yun ping
Jason Zhu
Shawn Lin
David Wu
Steven Liu
Simon Xue
Zain Wang
Jianqun Xu
Finley Xiao