qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
51,349 Commits 1 Branch 0 Tags 137 MiB
Commit Graph

13801 Commits

Author SHA1 Message Date
Yifeng Zhao 5f73fdb14a rockchip: rk3568: support usbplug 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If2c56d1db774f79689cfbe87bcae7cfcadacae82
 2021-02-04 20:34:20 +08:00
Yifeng Zhao da041cba1f arch: rockchip: add set dfu alt info api 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Idc6bd66c5b85a2bb100da3f270dd86b48dec8886
 2021-02-04 17:27:41 +08:00
Joseph Chen f345af8b36 rockchip: rk3568: add AArch32 build support 
SPL and TPL is still in AArch64 mode.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I4768903d1dbdd06359eb196607b67fb128dea644
 2021-02-04 15:05:57 +08:00
Joseph Chen a225402cf7 rockchip: board.c: support reboot stess test 
It's a way to test system stability before kernel stages.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6679fbbbaa7233750b409b6b832849d8dbd36893
 2021-02-03 09:52:53 +08:00
Lin Jinhan f54f4b43d9 rockchip: dts: rv1126: modify rng & crypto node 
The RNG driver is separate from the Crypto driver.

Change-Id: I51b39e337106988d5444246a53e46c27644effb0
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-01-30 09:50:09 +08:00
Patrick Delaunay dd239d3008 UPSTREAM: arm: armv7: solve issue for timer_rate_hz in arch timer 
The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.

With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
(cherry picked from commit 77aace579a9a84c74e99d2e86ecc08b1d9ca402b)
Change-Id: Id289de433e49d396a95e3a72acf210be3a2d910b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2021-01-29 18:52:41 +08:00
Lin Jinhan 529dfdedda rockchip: dts: rk3568: add rng node and enable 
Change-Id: Ie58d30776facf7f2bd6060fad06c4cbb53727e68
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
 2021-01-29 17:50:52 +08:00
William Wu b23020efaf rockchip: rk3568: set usb2 phy0 and phy1 in suspend mode 
This patch set the USB 2.0 PHY0 port0 and PHY1 port0 and
port1 in suspend mode to save power. And set the USB 2.0
PHY0 port0 for OTG interface still in normal mode.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I684e3bf8ce7934402e745ea7cfe110b987f5d9db
 2021-01-28 15:04:41 +08:00
Jon Lin f7a0277a1d rockchip: rk3568: Enable FSPI secure 
Change-Id: Id46debc74bfac7060244079582b06b35817b51cd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-19 15:54:36 +08:00
Joseph Chen 5e0c61290d rockchip: resource: add gpio-v2 support for hw-id dtb 
It's for rv1126/rk356x.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5a58483e43154c8ba61be466214f87753e47dd3
 2021-01-17 15:36:06 +08:00
Joseph Chen a39ea68564 rockchip: rk3568: select ARM_SMCCC to enable psci reset 
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1887d599e6219541c11e7a087a2a7480589244f6
 2021-01-16 12:08:46 +08:00
Tang Yun ping c69667e0e2 drivers: ram: sdram_common: add os reg v3 define 
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I2cedcddcebdfd32da113edd1e18d2498b5813e22
 2021-01-14 11:39:53 +08:00
Tang Yun ping a903774da2 rockchip: dts: rk3399: update dmc node for new sdram_cap_info 
new sdram_cap_info add cs2,cs3 row info

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Ia7eab3d473dbc8d98a277df6cffefe99463967f3
 2021-01-13 16:54:06 +08:00
Tang Yun ping 59b9aa0550 rockchip: dts: rk3328: update dmc node for new sdram_cap_info 
new sdram_cap_info add cs2,cs3 row info

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Id276447507752c581632d9d92a0524f2ba276dd8
 2021-01-13 16:50:29 +08:00
Tang Yun ping 1a6462e18b drivers: ram: sdram_common: add 4rank support for sdram_cap_info 
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Icda7bdc73e6c36c1351f0671b374a9d906dafec8
 2021-01-13 16:36:10 +08:00
Yifeng Zhao b1c0e43cef vendor: rockchip: fix mtd write issue 
The page offset is need point to empty page.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ib677e2937fd39b4b56622066cecfbe9a0da297ce
 2021-01-13 14:51:58 +08:00
Jason Zhu b0760df876 rockchip: dts: rk3568: set the sdmmc0-det pin pcfg_pull_up 
Since the sdmmc0-det is set to pcfg_pull_none and there is no sd
card, it has a current loss of 2 mA.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ifb6184d134155a39dc6986632a8346ffc342263f
 2021-01-13 09:01:05 +08:00
Joseph Chen d6ea9a1563 rockchip: rkimg: remove unused variables 
fix compile error.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3202eb2eab89a3530d0170fe9b0b7f890aec1f3a
 2021-01-11 14:11:27 +08:00
Jon Lin aa6eaeb21f rockchip: dts: rk3308: Add spi node 
Change-Id: I73568c5355e9acb6a92887992e3c8dca371ab455
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-11 11:29:20 +08:00
Joseph Chen d84179b5cb rockchip: make_fit_boot: add lz4 kernel support 
Don't handle ramdisk.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id8c04a6d916a8fd4ae1f3154c75e597c3e6980bc
 2021-01-09 08:41:06 +00:00
Shawn Lin 0b6867032a rockchip: dts: rk3568: enable pcie30 for NVMe boot 
Change-Id: I2095cec09f765572101353bc21507a82ba71c160
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin cda11ee6a9 rockchip: rk3568: Map PCIe MMIO regions for CPU 
Change-Id: Ieb5ce1ae68e26beba9b1e73548c5db630deb1487
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Jason Zhu 6f71993b11 rockchip: dts: rk3568: add max-frequency for sdhci 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I0815514fe2eeed99c73ac181f1ce42c89f7644c9
 2021-01-07 09:23:44 +08:00
Jason Zhu f2e13b14c7 rockchip: arm: dts: rk3568-spi-nand: create this dts for spi nand device 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie6412cf8d5227ddd0f580d129cca77236d1c5bff
 2021-01-06 15:29:45 +08:00
Yifeng Zhao 5beee4e829 arch: rockchip: fit misc: fix complie error 
arch/arm/mach-rockchip/fit_misc.c:26:12: error: ‘fit_image_check_uncomp_hash
defined but not used [-Werror=unused-function]

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If959d9e946351ce41dd1374b4c69f182f5273d39
 2021-01-06 14:54:48 +08:00
Joseph Chen 5ead1aa09a rockchip: spl: only allow do reset after dm setup 
Without this, there is a dead loop path:

hang() => spl_hang_reset() => do_reset() => failed to reset => hang()!

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8553bde97bd45ca63e5a12aca1acfc939301b04f
 2020-12-31 14:40:33 +08:00
Joseph Chen 1d22de7f19 rockchip: rv1126: rename periph device region 
Adding to whitelist.txt:
	CONFIG_PERIPH_DEVICE_START_ADDR
	CONFIG_PERIPH_DEVICE_END_ADDR

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia07a467489e52b7580351829768437dc67e71833
 2020-12-30 17:48:20 +08:00
Joseph Chen 2708ed29a4 rockchip: fit: update gunzip() max image size to 2MB 
RK3568 U-Boot is over 1MB size.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ibe2000e4472c57c8d91b38b1fc2ce3d23c27a3db
 2020-12-30 17:34:45 +08:00
William Wu edaca8fc29 rockchip: rk3568: assert reset the pipephys to save power 
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ie2df9df2a7312debf215276450476537f5c29bad
 2020-12-30 16:04:06 +08:00
David Wu 34ddf661ae arm: dts: rk3568: Add gmac node 
Change-Id: Ie75274260889afa7cb5aa1b3814d691542358974
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-12-29 18:06:54 +08:00
David Wu 2a2aae6ca3 arm: dts: rk3568: Fix typo in gmac1_clkin 
Change-Id: Ice4a313d004fa9f9b193d7258b0216187a4e5be2
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-12-29 18:06:54 +08:00
Jason Zhu ee7b0fb8d5 rockchip: board: fix initial otp index as again and again 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ib520b342edd6e404d8bb4167d0280e8589f38fb4
 2020-12-29 14:56:56 +08:00
Jon Lin 1e5036b9d9 rockchip: vendor: Support MTD SPI Nor 
Change-Id: I67d01db2d335abfd483596a2f7033d1e38cffaf5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2020-12-29 14:45:29 +08:00
Tang Yun ping 9ff9a8fead rockchip: rk356x: setting ebc priority to 0x3 
Enable all power domain except npu and gpu.

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I3757b8770b6d5a2a96b9d0945bbe536b6d387741
 2020-12-29 14:43:52 +08:00
Steven Liu ee1765b515 rockchip: rk3568: fix uart iomux error. 
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ib1683c8ef40127b4fb5b0feb18778b85da47fe03
 2020-12-28 16:36:57 +08:00
Simon Xue cce5b40859 rockchip: dts: rv1126: enable wdt 
Change-Id: I6d66dd8fca6beaf90557af048e4a50aaabe788d5
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-12-28 16:19:25 +08:00
Simon Xue e197a0baf5 rockchip: dts: rk3568: enable wdt 
Change-Id: I73c34bcdd68cdd30dc07c688331ba9fa284159e7
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-12-28 16:19:25 +08:00
Joseph Chen 4d85f76c54 rockchip: kernel dtb: fixup cru phandle of "resets" property 
Mainly for wdt in U-Boot.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I80946bf85015b84d8ea4db95fc00b314160505f8
 2020-12-28 16:19:25 +08:00
Simon Xue 63ea025947 rockchip: dts: rk3568: wdt add reset 
Change-Id: Ib18ae7bc9c83cdd42e4e444b598072f81d2d48c0
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-12-28 16:19:25 +08:00
Simon Xue 6d2b3a9a8d rockchip: dts: rv1126: wdt add reset 
Change-Id: I86d24ce0476dcc898dd5f12d6e5039a13358c76b
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-12-28 16:19:25 +08:00
Zain Wang bcec45798d rockchip: board: Do not set unvalid index to rollback-index 
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Change-Id: I2ba9c666c8375e02569518db9604d214c2a23b53
 2020-12-28 15:10:23 +08:00
Jianqun Xu c571b46d59 ARM: rockchip: rk1808 set gpio0_C2 to pull down 
It's a long story to explain why to set gpio0_c2 to pull down, start
from ...

The rk1808 suspend supports to swith 32k clock source, BUT need the
low level for each source clock.

clk_32k  ---  ext_32k from pmic for example (pin on SoC is AWK13)
         |
	 ---  int_32k divided from 24MHz

The pin AWK13 default to be GPIO0_C2 which is normal state defaultly.

When the software try to switch clk_32k from int_32k to ext_32k, but
the pin is in normal state, unluckly for some board it's high level,
the result is the switch never be done, till device try to do suspend
and into a halt state.

Make the gpio0_c2 to be pull down as default state for kernel.

Change-Id: I6ae5859352d9a680166b4c711e25491a60442209
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-12-28 14:51:09 +08:00
Jason Zhu a432abd525 rockchip: rk1808: fix typo 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I117c754994afc73a1c57274593ddc216273344d8
 2020-12-28 14:47:57 +08:00
Jason Zhu bf39446f5d rockchip: spl: support rollback index 
Support rollback index when enable CONFIG_SPL_ROCKCHIP_SECURE_OTP.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id865d9b13f92a322b576dd0168805e05acbdbcbf
 2020-12-28 14:13:01 +08:00
Jason Zhu a31e24f37f rockchip: fit_misc: use OTP_SECURE_BOOT_ENABLE_ADDR to get vboot address 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I464f6834d3ec2cb653e5149ab2f9abd3bbcc1724
 2020-12-28 14:11:57 +08:00
Finley Xiao 2bff5c680e clk: rockchip: rv1126: Only change APLL rate to 1008MHz for tb 
fixes: (c1bad47 clk: rockchip: rv1126: Change APLL rate to 1008MHz)

Change-Id: If0c284af8c5710b43d353fdf6b12b226c288ae07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2020-12-24 15:06:36 +08:00
Jason Zhu 3a5404aff4 clk: rockchip: rk3568: set the APLL_HZ to 816MHz 
Set the APLL_HZ to lower frequency in spl when the pmic is not
available.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id540ff174ef93c3d9ea22bb37dc26ca7b587a5b7
 2020-12-24 10:00:10 +08:00
Zhihuan He 355cdcf345 rockchip: rk3308: coding style 
Change-Id: If0404baf3019317e2dcf9a6c8a77e8a82a13f888
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
 2020-12-23 18:13:34 +08:00
David Wu 2cde40a19f arm: board: Random way to change multiple mac addresses 
Change-Id: I11f93717fae567daaba4801979fb38c74e7b4e83
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-12-23 15:31:13 +08:00
YouMin Chen 3c13acb0a2 rockchip: sdram_msch: update noc define for rv1126 
Change-Id: Ic545cacffabc0c726d6d0de3e6d72a3e6c971849
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2020-12-21 16:47:27 +08:00