CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
(cherry picked from commit ee1e600c13d16febd517ab7d0d2c243db174789b)
Change-Id: I564708bb6517b699749e8a54c013d032f785e459
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
ATMEL_SPI is now fully converted to driver-model and
respective boards switch to DM_SPI as well,
so make default y for ARCH_AT91
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
(cherry picked from commit 89d4fc153bb5c3830ab9e75e1690738cccea0322)
Change-Id: I3c3da47c05f7fef7a2129c5325c4ddf7b596b2cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h
Change-Id: Ia43a1c2dc2fc7e02a7d5613c8aac31c63bd0c37c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 37434db29be495ef41f204a97b8bf13b1418f97d)
All board configs are now enabled DM_SPI for SPL and
U-Boot proper, so now its time to drop non-dm code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
(cherry picked from commit 7b0947787358c6b277431d6b76ce043d8bec641d)
Change-Id: Ifa87682ea641368d73be6a059c00d194a668bf4b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.
Change-Id: I12cb7f90bd11ca5687da7992382fb3b447d5ec1c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9bf48e2ee8a0174adfb0f18d110198e4ca042284)
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Change-Id: Icfcb73b19f630bda5faf2d8bbb03efff6db9c933
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 63018a3eddd5d9c64f7ee42615a63c6a67ab484d)
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Change-Id: I3e52a45a49f96177d1c0d3781d8d98d7df5d9e0c
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4b5f6c52e78d43710a0d062e31de741ec76ceea1)
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Change-Id: Ifecfe693bdc9316da7d23db43f8764885e3cb786
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit bcdcb3e61ebd0550355883aed3978028d0e7778b)
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Change-Id: I2654951199094c51609c5402b5abd62438bbf1dd
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d3d8aaec7401703079f296a6460fe649fb06581b)
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Change-Id: I876d86fbf05feccebf6ded5f3acfa09a6cd15ea2
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fc282c7bcb6a622ce1a0cf82c55654dec5bcb0cd)
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Change-Id: I13be86b6b7da544ff64656fdb62ea79d5ee16d26
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c6b4f031d96a4e1d59761b294829b058b098f3df)
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
struct udevice *bus = dev->parent;
Change-Id: I6413fbdc32b1365d545033382c40fa39f85e5b84
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b2b41d27775823b8e19f6816aa08ffca0e234ade)
set_mode, set_seed functions has separate function pointers
in dm_spi_ops, so use them in relevent one instead of
calling from claim_bus.
Change-Id: Ifbe121f3a84c8b2ce007fe5a80fdd213b9f78a82
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 84807922874e03895bbf15c4472a2dcee8fbbd03)
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig
already enabled DM_SPI, so non-dm code make no use
of it hence droped.
Change-Id: I6864c71a8e9a97619fbe1989856077285aa2408e
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 15927aef02b7e7b5921bd1470ce145c2fa03ef08)
Change-Id: Ia9f6139d87f28ef8bbab5effb15b3e00e53e732d
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fbca0e66cc982325d8031094736d79ed007e42e2)
Change-Id: I70b43d668f905f236e18493c07ac6c369b7ca2d1
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4a942f49b891872727aa0bdba58e2ca513fc455c)
Change-Id: Ib34e1271ed6dd812bfb21bc2162b30d27b014498
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2c4b096b4c3e9d115b43edb23b1592a297076ae4)
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
(cherry picked from commit bbdf38698ee5c96138868d563c6825cd48bb26dc
Change-Id: I6c99c0696716c148a9f8a3255111b23749c78a6b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: Id2769d0405f96348de67cdd24df8a82a35101637
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7b819b569e92fd9b9b1baf160cd946a523fde1ce)
Change-Id: I51b0a222d7f5d4bf8925f7544c50d8f35da235e2
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a5dfabea19f961826509118513f833cea25797bb)
Change-Id: I66c533e5c556c26b771037bc7eee5ceff01f5cb9
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 95d3877a5818cc3f149a9d443637ff145bbaaabb)
Check if ns before and not after dereferencing it.
Indicated by cppcheck.
Change-Id: Ic9a2491051754fef64ce7ad4a9a5377fc3aad6db
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 923837e159c5886be38c7a83a2d6bc489b35c1f4)
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.
Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)
Reviewed-by: Marek Vasut <marex@denx.de>
Change-Id: Iee14939326b5512a7704ccbcfd9795d1a1f6aa3b
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 58c125b9e2b232ce73ed7b24ba7b1ca5ff41c5bd)
This reverts commit 57897c13de.
Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
(cherry picked from commit a743e2ba3837db5e8499b03f0f57c3610d03a570)
Change-Id: I793c697ad11d10259e233b2a6b0fe6e6f0b3df85
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This reverts commit b63b46313e.
This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.
Change-Id: If32c692ac37cf2ee25254b7ecc49bc09096bf5d0
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 948ad4f07598a729a0de523ed3d779115b2fa2f2)
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.
Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>
Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Change-Id: Ic221ac76abf1a32a027b9650bc6f27667209c77c
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 15a70a5da33229de884f60684a562ea60fe505b2)
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz. However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.
Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.
Change-Id: Iee0b8cb304816d74c6442132be4cc04e6cb8adbc
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit df16881cea50a787c37591bd2168c8ea656217bd)
Remove a superfluous newline, and reduce the scope of a variable.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I8916ae85b0339d29d7b50382182a263848e21a39
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 24fc1ec2ee71cd852e556f90bd352cc809ddeef9)
A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.
This patch removes the function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I0836438bec6597bb99038997ae6a549d647f1666
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 184fa1c8da54d3c5305b3e1975e284e01de68bea)
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT
node") added a helper function spi_base_setup_slave_fdt to to set up a
SPI slave from a given FDT blob. The only user was the exynos SPI
driver.
But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed
the use of this function, hence rendering it obsolete.
Remove this function, as well as the CONFIG_OF_SPI option, which guarded
only this function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I2a5bd866fda6d65b908c1f71160da59ab5332a15
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c5b88f29ba46997e1cae39153980cae475b87b82)
This patch fixes a printf specifier style violation, reduces the scope
of a variable, and turns a void pointer that is used with pointer
arithmetic into a u8 pointer.
Change-Id: I4084bfeaba1e992f589f5190660bcbfb8627b0b3
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 547bcc3d18ddcc107b8aa7ca393830590c27978f)
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
Change-Id: Ib6d47452d3699df5eb799cc0289687331192f380
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 29cc4368ad4b8d67ae457681e9249e2008d6fee5)
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
Change-Id: I2a36ddc619bc5801fe6f9f9873a63d8e6d62534f
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5ac07d2969e7f1ea2582f97ccacbe9ad9c9d62fc)
This converts the following to Kconfig:
CONFIG_DAVINCI_SPI
Signed-off-by: Adam Ford <aford173@gmail.com>
(cherry picked from commit 26410c1517bbb6d6f90de55b5fa65dac3c298bc7)
Change-Id: I7b2166d5ea20dcd0a0e79d6faa1c51fca4d6eef9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.
Add the compatible entry for 6ul/7d.
Change-Id: I8aa660b610b39c24969560187b35d5e7a8a17f5d
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit afe8e1b03362f169b2f905d20e2b352aca9d522e)
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.
Change-Id: I932c2ed047541b6ad09344c0ceb80496ac575c64
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6720e4ae7a01afa93b99a8f62b0cc98fe01abc9b)
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.
Signed-off-by: Rick Chen <rick@andestech.com>
(cherry picked from commit 41bbb8b333a6977cd28d31c58a5a209001ce5056)
Change-Id: I78d0112ba78c09ba9cd2beace324b3af9b867d71
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
fix typo
Change-Id: If467ba2cb4d16a4844400e9046e851ab0b96a4de
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 11f12c17d72499292f6e219ebbf8062faedcc5bb)
fix typo
Change-Id: Ifee202f67e4a972854ed33745de3984b6ae9e2d1
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 042de609ed49cfc41afb13639850c7b01079a527)
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.
Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.
Change-Id: I2cef052b87320392449c39a8aa2330236539a2c3
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ab20107468de5bf6b9affa93b17f2284cc838b5b)
The DM support is already in the driver, so add
da830-spi to the compatible list.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I1a9146dc21017f7f32e79608cfecb4129df93a14
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ab0ac272421c4b72c7a78db32ad709e23cab1eea)
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.
Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Change-Id: I87e05aa2d038997a6681d664605c0de9ca6d51bd
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 10509987285515b0a969c39ef7374fea3545851b)
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
(cherry picked from commit 1c631da459a82f4f82a063f5b4ff339ca5384d11)
Change-Id: I79b786b7e24294538cf014c86658838409c29e78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.
Change-Id: Idb04e59b28f570b161aa75216748ebda0ed6d9ac
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 994266bdff7903279b8e43ddbf220b04a4e1411f)
This patch update the behavior introduced by
commit 96907c0fe5 ("dm: spi: Read default speed and mode values from DT")
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_* but instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Remove also use in boards of the value speed=0 (no more supported)
for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0.
DT values will be always used when available (full DM support of
SPI slave with available DT node) even if speed and mode are requested;
for example in splash screen support (in splash_sf_read_raw)
or in SPL boot (in spl_spi_load_image).
The caller of spi_get_bus_and_cs() no more need to force speed=0.
But the current behavior don't change if the SPI slave is not
present (device with generic driver is created automatically)
or if platdata is used (CONFIG_OF_PLATDATA).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Change-Id: I6f5990b73f33815a7acb9b5da9c90dce48b6211d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b0cc1b846fcb310c0ac2f8cbeb4ed5947dc52912)
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I4c459ebdff8b2aec38623f27d0ba630c6c6f1ca3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c4e8862308d420e85c227498797c32410d9e47a8)
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Change-Id: I912b535ef05862f65e535ba828b680a07cd784d3
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6430eea639ed9ca967764a0ee113fa1c53619356)
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.
Change-Id: I27bb7e70536178101e26c28b28d1c64b0d07f064
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 76094485e462d1bed6c37ed465d1fcb341d94531)
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I22b4bf3f6f35de38297aa86edd38d4bc401fb23e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 12563f768ed7357d52bc15773b76cbeca6407d92)
Christophe Leroy
Jagan Teki
Sjoerd Simons
Eugeniy Paltsev
Tuomas Tynkkynen
Heinrich Schuchardt
Vignesh R
Goldschmidt Simon
Jason Rush
Chris Packham
Mario Six
Álvaro Fernández Rojas
Adam Ford
Peng Fan
Rick Chen
Bin Meng
Suresh Gupta
Patrick Delaunay