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51350 Commits

Author SHA1 Message Date
Jon Lin 2a2a073c3c mtd: spinor: mx25u25635f enable quad read 
Change-Id: I66ef7cf13b58b1a3c2a4e8ea78c1c3a8090c57df
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-19 10:00:57 +08:00
Jon Lin 8c4105cc49 mtd: spinand: Support BWJX08K 
Change-Id: Iddcc569cb4865bc73d0829fd5e6a33c7c85632b5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-19 10:00:49 +08:00
Jianqun Xu bd3ad955a3 scripts/dtc: phandle index start from 0x1000000 
Change-Id: I1141545e4592bfebf812f2477d1851d178ee8bd8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2021-01-18 10:24:07 +08:00
Jon Lin 69bb6ffab4 mtd: mtd_blk: Only reserve for last partition with grow tag 
Change-Id: Icd3bd87b45bdb3af6688269a2332463f570f4d46
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-18 09:03:19 +08:00
Jon Lin ce9d2743ba mtd: mtd_blk: spinor reserved area aligned to 64KB 
1.reserve for GPT
2.kernel spinor erasesize is 64KB

Change-Id: I32a5b26f8f39b4b226ec54342ce5d8d3d71f1c4d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-18 09:03:19 +08:00
Joseph Chen e3a5bc90c0 rockchip: rk3568: add distro boot support 
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id1edbf251a363698f07b2b9c069fd0890c7c55ff
 2021-01-17 16:03:55 +08:00
Joseph Chen 5e0c61290d rockchip: resource: add gpio-v2 support for hw-id dtb 
It's for rv1126/rk356x.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5a58483e43154c8ba61be466214f87753e47dd3
 2021-01-17 15:36:06 +08:00
Joseph Chen a39ea68564 rockchip: rk3568: select ARM_SMCCC to enable psci reset 
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1887d599e6219541c11e7a087a2a7480589244f6
 2021-01-16 12:08:46 +08:00
Wyon Bi d63e2d24c5 video/drm: analogix_dp: Fix voltage_swing/pre_emphasis level calculation 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I07a071b77a254cbe940b4df4dd6b52b069339076
 2021-01-15 15:58:04 +08:00
Tang Yun ping c69667e0e2 drivers: ram: sdram_common: add os reg v3 define 
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I2cedcddcebdfd32da113edd1e18d2498b5813e22
 2021-01-14 11:39:53 +08:00
Tang Yun ping a903774da2 rockchip: dts: rk3399: update dmc node for new sdram_cap_info 
new sdram_cap_info add cs2,cs3 row info

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Ia7eab3d473dbc8d98a277df6cffefe99463967f3
 2021-01-13 16:54:06 +08:00
Tang Yun ping 59b9aa0550 rockchip: dts: rk3328: update dmc node for new sdram_cap_info 
new sdram_cap_info add cs2,cs3 row info

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Id276447507752c581632d9d92a0524f2ba276dd8
 2021-01-13 16:50:29 +08:00
Tang Yun ping 1a6462e18b drivers: ram: sdram_common: add 4rank support for sdram_cap_info 
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Icda7bdc73e6c36c1351f0671b374a9d906dafec8
 2021-01-13 16:36:10 +08:00
Yifeng Zhao b1c0e43cef vendor: rockchip: fix mtd write issue 
The page offset is need point to empty page.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ib677e2937fd39b4b56622066cecfbe9a0da297ce
 2021-01-13 14:51:58 +08:00
Weixin Zhou 39c952ae4e video/rk_eink: add poweren for tps65185 
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: Icc6059a723f9e5d0b90c623497f0b03adea9e726
 2021-01-13 11:40:59 +08:00
Finley Xiao fd7b518283 rockchip: otp: Add support for rk3568 
This adds the necessary data for handling otp on the rk3568.

Change-Id: Id5e8a3a1561604bb307ef17e06d11d7e62d8a840
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2021-01-13 09:32:47 +08:00
Jason Zhu b0760df876 rockchip: dts: rk3568: set the sdmmc0-det pin pcfg_pull_up 
Since the sdmmc0-det is set to pcfg_pull_none and there is no sd
card, it has a current loss of 2 mA.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ifb6184d134155a39dc6986632a8346ffc342263f
 2021-01-13 09:01:05 +08:00
Wyon Bi 8d52d662b5 clk: rockchip: rk3288: Fix i2c clk rate calc 
Change-Id: I083e2b8ceaa3eee7729174aa2e17b8a08cec9c05
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2021-01-13 09:00:50 +08:00
Joseph Chen d6ea9a1563 rockchip: rkimg: remove unused variables 
fix compile error.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3202eb2eab89a3530d0170fe9b0b7f890aec1f3a
 2021-01-11 14:11:27 +08:00
Jon Lin aa6eaeb21f rockchip: dts: rk3308: Add spi node 
Change-Id: I73568c5355e9acb6a92887992e3c8dca371ab455
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-11 11:29:20 +08:00
Jason Zhu e6d86e0023 configs: rv1126-spi-nand: reduce the code size 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I4c9273ad1cbbe0730c7057e932a55075ff6e1942
 2021-01-11 11:28:36 +08:00
Jason Zhu a2875f15a8 dm: blk: fix spi flash uclass different error when use mtd block 
Add more condition to decide which dev is "mtd 2".
More info seen in 82ee425415.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iea84b5a7307969dad785f3136b0af8b9f45e94f6
 2021-01-11 11:12:58 +08:00
Joseph Chen d84179b5cb rockchip: make_fit_boot: add lz4 kernel support 
Don't handle ramdisk.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id8c04a6d916a8fd4ae1f3154c75e597c3e6980bc
 2021-01-09 08:41:06 +00:00
Shawn Lin fae486e407 power: regulator: Use dev_read_size in gpio-regulator 
Change-Id: Iff2e643d6dad6975fe0838dc439a31ecd5299f41
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-08 09:24:05 +08:00
Jason Zhu ec7aa9fc77 configs: rk3568: redefine the CONFIG_FASTBOOT_BUF_ADDR 
According to the CONFIG_SYS_LOAD_ADDR.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie2679791283618a9b86447ac26a0d2ef7574eb86
 2021-01-08 09:22:21 +08:00
Jason Zhu b822206b1f configs: rk3568-nand: reduce the code size 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Icc72cf5af4a843ec3f721d538085d2870e47ecbc
 2021-01-07 10:39:27 +08:00
Yifeng Zhao 7cd717205f drivers: rknand: zftl: fix to support samsung ss14 8GB NAND FLASH 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I86d47db8988b56d36ae76d08997c840b34f0b0d8
 2021-01-07 10:39:27 +08:00
Shawn Lin bc58f2110b drivers: pci: Add Rockchip DesignWare based PCIe controller 
=> pci enum
PCIe Linking... LTSSM is 0x1
PCIe Link up, LTSSM is 0x230011
PCIE-0: Link up (Gen3-x2, Bus0)

=> pci scan
Scanning PCI devices on bus 0
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
_____________________________________________________________
00.00.00   0x1d87     0x3566     Bridge device           0x04

=> pci 1
Scanning PCI devices on bus 1
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
_____________________________________________________________
01.00.00   0x144d     0xa808     Mass storage controller 0x08

=> nvme scan

=> nvme details
Blk device 0: Optional Admin Command Support:
        Namespace Management/Attachment: no
        Firmware Commit/Image download: yes
        Format NVM: yes
        Security Send/Receive: no
Blk device 0: Optional NVM Command Support:
        Reservation: yes
        Save/Select field in the Set/Get features: yes
        Write Zeroes: yes
        Dataset Management: yes
        Write Uncorrectable: yes
Blk device 0: Format NVM Attributes:
        Support Cryptographic Erase: No
        Support erase a particular namespace: Yes
        Support format a particular namespace: Yes
Blk device 0: LBA Format Support:
Blk device 0: End-to-End DataProtect Capabilities:
        As last eight bytes: No
        As first eight bytes: No
        Support Type3: No
        Support Type2: No
        Support Type1: No
Blk device 0: Metadata capabilities:
        As part of a separate buffer: No
        As part of an extended data LBA: No

=> nvme info
Device 0: Vendor: 0x144d Rev: EXD7201Q Prod: S444NA0M384608
            Type: Hard Disk
            Capacity: 244198.3 MB = 238.4 GB (500118192 x 512)

=> nvme device 0

=> md.l 0x40000000 1
40000000: d08ec033                               3...
=> mw.l 0x40000000 0x55aa55aa
=> md.l 0x40000000 1
40000000: 55aa55aa                               .U.U

=> nvme write 0x40000000 0x0 0x1

nvme write: device 0 block # 0, count 1 ... 1 blocks written: OK

=> md.l 0x44000000 1
44000000: ffffffff                               ....
=> nvme read 0x44000000 0x0 0x1

nvme read: device 0 block # 0, count 1 ... 1 blocks read: OK

=> md.l 0x44000000 1
44000000: 55aa55aa                               .U.U

Change-Id: I645dfc7e88722e9948ecb6e1a3a589eb4b420c1f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin 76ab734171 phy: Add Rockchip Synopsys PCIe 3.0 PHY 
Change-Id: Ie29e4777f8f0603b779cc3387dc5c4b63336deff
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin 80907d3c4c core: device: Add PCIe to bind list if we set GD_FLG_RELOC 
Change-Id: Ib115bc6eb52f8a08e28805ea15e2cbf8f27f5f63
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin 0b6867032a rockchip: dts: rk3568: enable pcie30 for NVMe boot 
Change-Id: I2095cec09f765572101353bc21507a82ba71c160
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin cda11ee6a9 rockchip: rk3568: Map PCIe MMIO regions for CPU 
Change-Id: Ieb5ce1ae68e26beba9b1e73548c5db630deb1487
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin d504dfb2b1 clk: rockchip: rk3568: Ungate PCIe30phy refclk_m and refclk_n 
Change-Id: I718f280cd78235131f3f3ef76e17e498a6e4db8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Shawn Lin cd282fabfa power: regulator: Migrate to dev_read_u32_array for gpio-regulator 
fdtdec_get_int_array_count is obsoleted and we should use
dev_read_u32_array for seeking node members.

Change-Id: I666bd7317cfa203229454d24c910049c24bf8a2f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-01-07 10:00:59 +08:00
Yifeng Zhao 1800dd0569 configs: rk3568: enable slc nand 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I885ce4eaf5ac0625e84e1a2195b477725edc6216
 2021-01-07 09:28:32 +08:00
Yifeng Zhao 813156ed32 drivers: mtd: nand: support slc nand for rk3568 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Id9bc21f8fb443574ad150c32b9c6980e2e038ca7
 2021-01-07 09:28:32 +08:00
Elaine Zhang 2f5dff11cb thermal: rockchip: support rk3568 
Change-Id: Icb4d127a9d9c3f599a141c69c7c759da6e38cf36
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2021-01-07 09:24:58 +08:00
Jason Zhu 6f71993b11 rockchip: dts: rk3568: add max-frequency for sdhci 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I0815514fe2eeed99c73ac181f1ce42c89f7644c9
 2021-01-07 09:23:44 +08:00
Jon Lin 43f2461c06 mtd: spinand: Add optional configuration for different devices 
Change-Id: If3d66f2f48f7322493175cdfba46d563b760b44c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-01-06 15:34:03 +08:00
Jason Zhu daa2653382 configs: rk3568: support mtd write in spl 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic0c4502bf202796df6138ccfb91a09636d6b99db
 2021-01-06 15:30:03 +08:00
Jason Zhu 0fb8f93bbb configs: rv1126: support mtd write in spl 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Idba0d10e80d6368a912d6369c85efb6eaa2212d6
 2021-01-06 15:29:57 +08:00
Jason Zhu 0554021750 configs: rk3568-spi-nand: reduce code size for spi nand device 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I6f47591f30ff4eb7b9bfa1830bf8060963c3a210
 2021-01-06 15:29:51 +08:00
Jason Zhu f2e13b14c7 rockchip: arm: dts: rk3568-spi-nand: create this dts for spi nand device 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie6412cf8d5227ddd0f580d129cca77236d1c5bff
 2021-01-06 15:29:45 +08:00
Jason Zhu 5b4dcfe0cf spi: rockchip_sfc: set clock depended on CONFIG_IS_ENABLED(CLK) 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Icb3662d97eeea8db1e1a62f633f9ba4de9b72dde
 2021-01-06 15:29:39 +08:00
Jason Zhu a0166cc6be mtd: Kconfig: add a Kconfig option to enable the support for MTD block write operations 
This allows using CONFIG_IS_ENABLED(SPLMTD_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ia48169fcd601ad51d1723923ed71d610901275e1
 2021-01-06 15:29:34 +08:00
Yifeng Zhao 5beee4e829 arch: rockchip: fit misc: fix complie error 
arch/arm/mach-rockchip/fit_misc.c:26:12: error: ‘fit_image_check_uncomp_hash
defined but not used [-Werror=unused-function]

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If959d9e946351ce41dd1374b4c69f182f5273d39
 2021-01-06 14:54:48 +08:00
Yifeng Zhao c7c3548ddf drivers: Makefile: add block layer while enable rknand 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I8fc7b3d27e32d767da3597d3d5b7a6aa4a48ca40
 2021-01-06 14:54:48 +08:00
Joseph Chen 791045ea0f common: android: AVB support lz4 kernel 
The key point is to get kernel compression type by:
bootm_parse_comp((void *)(ulong)hdr + hdr->page_size);

Because if hdr->kernel_address is set as decompress
address before this comment, android_image_get_kernel_addr()
would return error kernel offset, result in a wrong
compression type from android_image_parse_comp().

Tested successfully on RK3568 EVB board:
 - LZ4 Image + AVB full partition load
 - LZ4 Image + AVB separate load
 - LZ4 Image + none-AVB separate load
 - Image + AVB full partition load
 - Image + AVB separate load
 - Image + none-AVB separate load

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5385843f036b52eb7a286b7194852accfb52225
 2021-01-06 14:44:05 +08:00
Jason Zhu 1f5c7b6414 spl: fit: support decreasing 1 if verify fail when enable a/b 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I922b929ac37181f61e820b6c2b2de750e816a99d
 2021-01-04 19:23:48 +08:00
Jason Zhu 093f4d990f spl: ab: support decreasing 1 in spl 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie3bad33476e25bbcbf9d845abc87c6e075671e0c
 2021-01-04 17:12:44 +08:00