This allows using CONFIG_IS_ENABLED(SPLMTD_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ia48169fcd601ad51d1723923ed71d610901275e1
arch/arm/mach-rockchip/fit_misc.c:26:12: error: ‘fit_image_check_uncomp_hash
defined but not used [-Werror=unused-function]
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If959d9e946351ce41dd1374b4c69f182f5273d39
The key point is to get kernel compression type by:
bootm_parse_comp((void *)(ulong)hdr + hdr->page_size);
Because if hdr->kernel_address is set as decompress
address before this comment, android_image_get_kernel_addr()
would return error kernel offset, result in a wrong
compression type from android_image_parse_comp().
Tested successfully on RK3568 EVB board:
- LZ4 Image + AVB full partition load
- LZ4 Image + AVB separate load
- LZ4 Image + none-AVB separate load
- Image + AVB full partition load
- Image + AVB separate load
- Image + none-AVB separate load
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic5385843f036b52eb7a286b7194852accfb52225
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL
Change-Id: Ibb3836ed8713e491238460783a85ee1808770f66
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
(cherry picked from commit d6400c3f8520bb9a203fe397039279c80f093c27)
Without this, there is a dead loop path:
hang() => spl_hang_reset() => do_reset() => failed to reset => hang()!
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8553bde97bd45ca63e5a12aca1acfc939301b04f
Aim to reduce power consumption, cpll should be gated and the clocks
will mux to non-cpll.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If9d1b48cdb237cf38133523a4fc20fa6e87e8e62
If support a/b system in uboot, please slect CONFIG_ANDROID_AB.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I7465bbfd5ed526805df02796674bdc1ef769aefb
Before this patch:
Flattened Device Tree blob at 08300000
Booting using the fdt blob at 0x8300000
With this patch:
Flattened Device Tree blob at 0x08300000
Booting using the fdt blob at 0x08300000
Change-Id: Ibd5f1cfc07791eff829512d1820eb3c8c0caa007
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
these flags will be used by other output interface, so remove
DSI special assign.
Change-Id: Ieb3a20e62c2b899e6757635eced86b85e1fb22f7
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This patch adds support for Analogix eDP TX IP used on RK3568 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba4e5fd15a35bdbaf373
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic60d8bb86a53f686e8c46323b58d099c727a36d3
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.
Add the DisplayPort phy mode to the generic phy_mode enum.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I472cc21ccf19ae55888085500bfad27787cc3074
Jason Zhu
Yifeng Zhao
Joseph Chen
Jean-Jacques Hiblot
Ziyuan Xu
Algea Cao
Wenping Zhang
William Wu
Jianqun Xu
David Wu
Jon Lin
Tang Yun ping
Guochun Huang
Wyon Bi