DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic60d8bb86a53f686e8c46323b58d099c727a36d3
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.
Add the DisplayPort phy mode to the generic phy_mode enum.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I472cc21ccf19ae55888085500bfad27787cc3074
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
be configured through the generic functions through a custom structure
added to the generic union.
The parameters added here are the ones defined in the MIPI D-PHY spec, plus
the number of lanes in use. The current set of parameters should cover all
the potential users.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If546789f44b477b9f46507e70ad9a59a4ab35288
The phy framework is only allowing to configure the power state of thePHY
using the init and power_on hooks, and their power_off and exit
counterparts.
While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.
That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).
So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.
phy_configure will actually apply that configuration in the phy itself.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Icd170eaef9a1dbe21e0c7664b797a27877c703b5
It is possible that users of generic_phy_*() APIs may pass a valid
struct phy pointer but phy->dev can be NULL, leading to NULL pointer
deference in phy_dev_ops().
So call generic_phy_valid() to verify that phy and phy->dev are both
valid.
Change-Id: I0d19180ae8524eb240f4afd6ea55d5d0f2907798
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 64b69f8c89352975c25730bcca4bf8af2296297f)
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.
Change-Id: I11c95af8c1b54f2dad41891f6d0edb8d9fac6606
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 4e1842988364446ba0cf2171d1eebb53c15bc44e)
It's a long story to explain why to set gpio0_c2 to pull down, start
from ...
The rk1808 suspend supports to swith 32k clock source, BUT need the
low level for each source clock.
clk_32k --- ext_32k from pmic for example (pin on SoC is AWK13)
|
--- int_32k divided from 24MHz
The pin AWK13 default to be GPIO0_C2 which is normal state defaultly.
When the software try to switch clk_32k from int_32k to ext_32k, but
the pin is in normal state, unluckly for some board it's high level,
the result is the switch never be done, till device try to do suspend
and into a halt state.
Make the gpio0_c2 to be pull down as default state for kernel.
Change-Id: I6ae5859352d9a680166b4c711e25491a60442209
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Support rollback index when enable CONFIG_SPL_ROCKCHIP_SECURE_OTP.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id865d9b13f92a322b576dd0168805e05acbdbcbf
Set the APLL_HZ to lower frequency in spl when the pmic is not
available.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Id540ff174ef93c3d9ea22bb37dc26ca7b587a5b7
Wyon Bi
Joseph Chen
Vignesh Raghavendra
Jean-Jacques Hiblot
Guochun Huang
Steven Liu
Simon Xue
Elaine Zhang
Zain Wang
Jianqun Xu
Jason Zhu
Jon Lin
Finley Xiao
Zhihuan He
Andy Yan
Sandy Huang
David Wu
YouMin Chen
Tang Yun ping