This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
Change-Id: I2a36ddc619bc5801fe6f9f9873a63d8e6d62534f
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5ac07d2969e7f1ea2582f97ccacbe9ad9c9d62fc)
This converts the following to Kconfig:
CONFIG_DAVINCI_SPI
Signed-off-by: Adam Ford <aford173@gmail.com>
(cherry picked from commit 26410c1517bbb6d6f90de55b5fa65dac3c298bc7)
Change-Id: I7b2166d5ea20dcd0a0e79d6faa1c51fca4d6eef9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.
Add the compatible entry for 6ul/7d.
Change-Id: I8aa660b610b39c24969560187b35d5e7a8a17f5d
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit afe8e1b03362f169b2f905d20e2b352aca9d522e)
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.
Change-Id: I932c2ed047541b6ad09344c0ceb80496ac575c64
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6720e4ae7a01afa93b99a8f62b0cc98fe01abc9b)
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.
Signed-off-by: Rick Chen <rick@andestech.com>
(cherry picked from commit 41bbb8b333a6977cd28d31c58a5a209001ce5056)
Change-Id: I78d0112ba78c09ba9cd2beace324b3af9b867d71
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
fix typo
Change-Id: If467ba2cb4d16a4844400e9046e851ab0b96a4de
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 11f12c17d72499292f6e219ebbf8062faedcc5bb)
fix typo
Change-Id: Ifee202f67e4a972854ed33745de3984b6ae9e2d1
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 042de609ed49cfc41afb13639850c7b01079a527)
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.
Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.
Change-Id: I2cef052b87320392449c39a8aa2330236539a2c3
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ab20107468de5bf6b9affa93b17f2284cc838b5b)
The DM support is already in the driver, so add
da830-spi to the compatible list.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I1a9146dc21017f7f32e79608cfecb4129df93a14
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ab0ac272421c4b72c7a78db32ad709e23cab1eea)
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.
Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO
Change-Id: I87e05aa2d038997a6681d664605c0de9ca6d51bd
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 10509987285515b0a969c39ef7374fea3545851b)
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
(cherry picked from commit 1c631da459a82f4f82a063f5b4ff339ca5384d11)
Change-Id: I79b786b7e24294538cf014c86658838409c29e78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.
Change-Id: Idb04e59b28f570b161aa75216748ebda0ed6d9ac
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 994266bdff7903279b8e43ddbf220b04a4e1411f)
This patch update the behavior introduced by
commit 96907c0fe5 ("dm: spi: Read default speed and mode values from DT")
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_* but instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Remove also use in boards of the value speed=0 (no more supported)
for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0.
DT values will be always used when available (full DM support of
SPI slave with available DT node) even if speed and mode are requested;
for example in splash screen support (in splash_sf_read_raw)
or in SPL boot (in spl_spi_load_image).
The caller of spi_get_bus_and_cs() no more need to force speed=0.
But the current behavior don't change if the SPI slave is not
present (device with generic driver is created automatically)
or if platdata is used (CONFIG_OF_PLATDATA).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Change-Id: I6f5990b73f33815a7acb9b5da9c90dce48b6211d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b0cc1b846fcb310c0ac2f8cbeb4ed5947dc52912)
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I4c459ebdff8b2aec38623f27d0ba630c6c6f1ca3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c4e8862308d420e85c227498797c32410d9e47a8)
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.
Change-Id: I912b535ef05862f65e535ba828b680a07cd784d3
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6430eea639ed9ca967764a0ee113fa1c53619356)
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.
Change-Id: I27bb7e70536178101e26c28b28d1c64b0d07f064
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 76094485e462d1bed6c37ed465d1fcb341d94531)
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I22b4bf3f6f35de38297aa86edd38d4bc401fb23e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 12563f768ed7357d52bc15773b76cbeca6407d92)
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.
Change-Id: I120f8ff89e1342fc615899d6e4b997d6d96e41c1
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6d373e523f899c5a8f8808327215e3b9eb3f92f4)
Some controllers are exposing high-level interfaces to access various
kind of SPI memories. Unfortunately they do not fit in the current
spi_controller model and usually have drivers placed in
drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
memories in general.
This is an attempt at defining a SPI memory interface which works for
all kinds of SPI memories (NORs, NANDs, SRAMs).
Change-Id: I5b907d51232777b54366a589a75b3b1ce1f54dd2
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e0bc8d8542f7bd34e5a6722d3ae41bcf9ca044af)
When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
information for read operations.
Change-Id: I58270e564a558fbaf9ae2c5b0d888d3af842e09c
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5e24a2ef8bf4f09b18cf4e943c73bfdd169a7581)
Add logging to aid debugging features in these drivers. Also drop some
code in sandbox_spi_xfer() which is not used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I736a761d9651dc17de0649f191ed717ea37a3fc6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c3aed5db591ee38068dc2b6d73b04638bd7b7b26)
wait_for_bit callers use the 32 bit LE version
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I638846de7db29711fb7c778cc8304b507de057fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 48263504c8d501678acaa90c075f3f7cda17c316)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The header file only used in sfc driver itself, so
we can move the all definition in header file to
the c source file.
Change-Id: I255a54e2570e79caea03287d8c6c8700d30e4fdd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The read/write mechanism of spi-nor are different:
For write: upper spi flash framework will split write request
page by page chunk, and the underlying spi nor driver must
handle all the chunk(chunk_len <= page_size) from upper framework
in one transfer, then the upper framework will check the flash_ready
status, then send next chunk.
For read: the upper spi flash framework will send all the
read request in one transfer, buf the underlying spi nor driver
may not be able to transfer them in one time(if trb > SFC_MAX_TRB),
so the underlying spi nor controller driver need to split the read
request at this condition.
Change-Id: I0a8970c066e41bbdb997909c7fefb96829318ce4
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Bounce buffer implementation takes care of proper data buffer alignemt
and correct flush/invalidation of data cache at once so we no longer
depend on input data variety and make sure CPU and SFC controller deal
with expected data in case of enabled data cache.
Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in
board configuration, otherwise corresponding library won't be compiled
and linker will fail to build resulting executable.
Change-Id: Idbd0499d7ce2baa9cbbb04ade97ddb5bf49952ac
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Store command/address/read write mode/which passed from
upper spi flash framework in independt var will make things
easier when handle it.
Change-Id: I65d645b2e1a53e18a7605c9496a6c43e938c91b4
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
When the SFC is in busy state, we wait for a while(timeout)
before reset it.
Change-Id: I3e8734126b6e3b1f9a2391ebe0f402635a18d76f
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
4 bytes aligned is required for dma transfer mode, so
switch to pio mode when get a non 4 bytes aligned transfer.
Change-Id: I66118b7380d10deed3a0c82a897e407fb96db5fc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Last user of this option went away in commit:
fdc7718999 ("board: usb_a9263: Update to support DT and DM")
Change-Id: I37d591ec0dc956e4ec26d17a5e8e2588cf5a1afb
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 95688de311e238ccfba21c50b1b67ceffbdc7fc5)
U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Change-Id: I921807c1770d36a91e692c48ab477558bb2ed0b8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 9b643e312d528f291966c1f30b0d90bf3b1d43dc)
Update the Rockchip SPI driver to support a live device tree.
Change-Id: Ib54a4e52ed7177f342aafdca1c6bc1ddc0b76eaa
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d27c273908c3ca534093e93d7730fc55973a02bc)
SFC stands for Serial Flash Controller on some
rockchip platforms such as RV1108 / RK3128.
This patch add support for it with Standard,Dual,Quad
mode.
Change-Id: Iaf60a789d4806371679fd0c0e1b2adf4fc04f85c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.
But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.
This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.
Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The OMAP3_SPI driver can work with or without DM_SPI. Moving this
outside of the #if DM_SPI section allows us to include it on boards
that don't support DM_SPI yet.
Signed-off-by: Adam Ford <aford173@gmail.com>
Pet the watchdog once upon each command call (qspi_xfer) and during
each loop iteration in several commands.
This fixes a watchdog reset especially during erase command.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update the tegra114 spi driver to support a live device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
Adjust this to take a device as a parameter instead of a node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.
This change is also coherent with the structure in kernel.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
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Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This change covers the rk_spi.c (SPI driver) used in Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas
Adam Ford
Peng Fan
Rick Chen
Heinrich Schuchardt
Bin Meng
Suresh Gupta
Patrick Delaunay
Vignesh R
Boris Brezillon
Simon Glass
Jon Lin
Andy Yan
Tuomas Tynkkynen
Masahiro Yamada
Philipp Tomsich
Tom Rini
Alexander Stein
Patrice Chotard
Stefano Babic
Christophe Leroy