Use common board file and move SoC spec setting into rk3399.c
Change-Id: Ic674cef566b16c33978a1430eadfa9438b2de1db
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use common board file and move SoC spec setting into rk3368.c
Change-Id: I1d5a2b0bae03f89092cc0daf1c52622b3884cc43
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use common board file and move SoC spec setting into rk3328.c
Change-Id: Ia7cf43e0096da980d744260caa61456ddc6b24eb
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use "uboot,spl-boot-orde" instead of "uboot,boot0".
Change-Id: I647500193ab7cd89e7e409b75793a3eff4453d84
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use common board file and move SoC spec setting into rk3288.c
Change-Id: Ie17232dd60d2b185b635631ce9373eb59b11c89c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c
Change-Id: Ie8caa63b898202ae588d5a71f130d14c741943a2
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We are going to remove rockchip_udelay after enable arch timer.
Change-Id: I8c7eea8315a42401d0fd7dbf1e4c812b5605bc73
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We don't need tpl for rk3066 after we enable this option.
NOTE: need to update code for clock init in boot0 later
Change-Id: I253e6a0fd3633d982ebabaa045a0d4839570bc6a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We add this for get the location for boot device of bootrom.
Change-Id: Ibf142129cacb09ed9e4e0084d003c6cc0812df54
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
STIMER is can only access in secure mode if the SoCs supports trust,
and it locate in alive power domain, as the source of ARM arch/generic
timer, we add a base addr for all SoCs so that we can init with a common
function.
Change-Id: Iab7b8706344ecdc635d66196eed1ff855afc9a24
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.
Change-Id: I4be3a801bf5537b94ed0c100cb44f49d78b8b15a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h
Change-Id: I98f8cffdbc990e3fcf19f41ca53ff5fd25155e63
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
In the function init_resource_list, if hdr is not NULL
The content addr is the sum of hdr addr and
(hdr->c_offset) * RK_BLK_SIZE. Then return 0 directly
without free hdr and content.
If hdr is NULL and gpt table is enabled, the parameter
offset must be multiplied by RK_BLK_SIZE and be divided
by RK_BLK_SIZE in function blk_read.
Change-Id: Ib4120745af8aa4924464f85c8bb4b34daee98fa6
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
This reverts commit 4a872f4aa8.
rk3229 evb and echo can not work with ddr52 enable.
Change-Id: Ia22b30ffe40de6f6e74e50ec5fd52e3715006de0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Freescale (NXP) boards have lots of defconfig files per board.
I used "imply PANIC_HANG" for them.
Change-Id: I56347810ee33ccd8bb3553b0ee95b858e827ce9b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 7e3caa81e0e9cc5e2beed4a3a1c334e2119f4498)
"ethernet" node fix-up for device tree happens before Linux boot.
There can be requirement of updating "ethernet" node even before
fix-up. So, add support of updating "ethernet" node.
Change-Id: I5fcde8776f7f0f5c7323b1340c69d346c9c01833
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 6bedf44714a145e09fddb8c5a03ada210b812ec9)
Only rk3399 atf need ROCKCHIP_SPL_RESERVE_IRAM. This commit updates
its default setting to 0 so that other SoCs do not need to define it.
Change-Id: I40e453451d5376ce15aede0859a7e5b336220094
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8a8106f06639314f750c9f8dc2b72df3925f7fbf)
Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not
need it.
The very beginning of U-Boot proper is different between armv7 and armv8:
armv7 start with ARM_VECTORS while armv8 start with 'b reset'.
Here is the map of very beginning for all cases:
armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS
armv7 U-Boot: ARM_VECTORS
armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399)
armv8 U-Boot: 'b reset'
Change-Id: I433ccd2e09f32fa3f1892953d67650a99dac39bc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 270288544e12c7c98e4bc9a5b121517ba0a959d2)
This patch extends pmic_bind_children prefix matching. In addition to
the node name the property regulator-name is used while trying to match
prefixes. This allows assigning different drivers to regulator nodes
named regulator@1 and regulator@10 for example.
I have discarded the idea of using other properties then regulator-name
as I do not see any benefit in using property compatible or even
regulator-compatible. Of course I am open to change this if there are
good reasons to do so.
Change-Id: Ifedf2c0a51cb725ddb290ee9dfd54a3fea45df70
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit bf802f5d544f85c03b4097ab23d078be43c61855)
Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18
without checking the return value of spl_relocate_stack_gd().
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Change-Id: I929a996608808934bf4d614acfffe43080594ecb
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Kever Yang <kever.yang@rock-chips.com>
CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit e421b646fce125ed92936628dc4b287de5f038a5)
To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.
Change-Id: I5ac722421b46514736d93452aab68debe8aabfe5
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 90351547ceeb76c1337757c51af0fb5a2c30bd02)
After relocation, when error happends, it is hard to track
ELR and LR with asm file objdumped from elf file.
So subtract the gd->reloc_off the reflect the compliation address.
Change-Id: I1db18049b1e895c74ec75ed6ce77231cf4f03bce
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 082693f4f02ad7a9de192e73feae34e28856b8e3)
In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.
Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.
Change-Id: I3d156413396f2a304773ef3a202f73d47cf65531
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 78ad457b2dbd0fe6cdc7ea42a69774a72ed007b9)
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Change-Id: I6132623ce069ec6c6cd59a01580e795142864862
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 4fc495e9e2e497afee383294a6ee9212e9a8bd73)
The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Change-Id: I4d6d7c51633eb7cd0fbfb1c6b7c501cf8c0fcf81
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd401abcd532c59cdaaf6ffeed762386c1813e58)
On the RK3399-Q7, we want to trigger a full platform reset (so the
various software stacks supported don't have to deal with the same
complexities over and over again) in case that anything other than a
power-on reset occurred.
To do so, this defines the /config/sysreset-gpio property and has it
point to a GPIO that will perform a power-on reset of the entire
platform.
Change-Id: Ic7e6b6871da4064c8ea4a5e62d5b55dfd80cf3e8
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 5f104178bf713615dc404fdfcf0fb53d89c66a07)
USB1 is connected to the on-module USB 3.0 hub and power to the hub
(actually it's a reset signal, modeled as a fixed regulator, that will
be released) should be enabled only during the first probing of the
device to avoid the hub from entering its low-power mode (where it
tries to attach on a fixed interval, but we always miss the timeslot
when U-Boot has the controller listening).
This adds a 'tsd,usb-port-power' stringlist to enable the
infrastructure in the board-specific usb_hub_reset_devices to find and
control the fixed regulator associated with control of the USB hub.
Change-Id: I6624aa6b0a847eb0d26013b5cda5e26edc3630f5
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 884ad05d34c49ac6c8e21346a63a627c6c9d4c52)
Same macros are defined in various places. Collect them into
include/linux/bitops.h like Linux.
Change-Id: I81d12e8c8151c6eb29499d2b5cd61ed782500492
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit ed3986ca30972c94f0076f88c948406ce030a05c)
The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable
to read and boot the system. pmufw is copied to the header data section
follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze)
and SPL runs on a53-0.
This is generated command line when PMUFW_INIT_FILE is setup.
./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin
Change-Id: I74fc17513dd99b876ab9c08ded6ad41a7b0cd3de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit c85a6b79d10ed8a098997370cbc4fb233ddcb13b)
The ROCKCHIP_BOOT_MODE_REG option defaults to a hex value, so 0 will
show as 0x0 if a default is provided and changed via Kconfig.
However, it still will show as 0, if no default is given.
Consequently, the "is set to something other than 0" test in a
Makefile is cumbersome. Instead this check can easily be performed in
the C-code.
This removes the ifeq-check from mach-rockchip/Makefile, adds a
matching #if-check to boot_mode.c and fixes resulting link issues (if
boot_mode.o was not included due to the Makefile check) by defining a
stub function (in case the functionality is not built in) for
setup_boot_mode in boot_mode.c.
Fixes: e306779 (rockchip: make boot_mode related codes reused across all platforms)
Change-Id: I5299469103d139a90b8c073779d872ef131c3b42
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit f07d76c00d1fe05baad1599d01d07a9226498923)
The RK3399 has a total of 9 I2C controllers. To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.
For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.
Change-Id: I7ad9400f05d3ee89263ecd2bcc391483934b6c74
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8c2bb589e29d5cb89e10c3ddd23b28d949fa9693)
This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that location is not
available, e.g. due to memory fragmentation loading other boot binaries or
firmware, splitting an SMP complex between various different OSs without
using e.g. the EL2 second-stage page tables to hide the memory asignments,
or due to known ECC failures.
Change-Id: I2fd535325517921c6036188b74ab4facd37b7118
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 49e93875a62fb9e96a4a7483b9bd5d8ae27ea76e)
Currently, pylibfdt is always compiled if swig is installed on your
machine. It is really annoying because most of targets (excepts
x86, sunxi, rockchip) do not use dtoc or binman.
"checkbinman" and "checkdtoc" are wrong. It is odd that the final
build stage checks if we have built necessary tools. If your platform
depends on dtoc/binman, you must be able to build pylibfdt. If swig
is not installed, it should fail immediately.
I added PYLIBFDT, DTOC, BINMAN entries to Kconfig. They should be
property select:ed by platforms that need them. Kbuild will descend
into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled.
Change-Id: I56c5daf252e28d23fcaea0bc2d327a34de60cdcf
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d6a0c78a4efb1353f4ec6f6c59c0771298510f58)
The VCC_SD and VCC_SDIO rail should only be powered up to 3.0V on RK3399
platforms.
Change-Id: I4b9adc8001b4d01f0ebd0d5a7a1bc2a050e82647
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 4f70039b360ae4645bc35c1d1a6cc41837ea161e)
pinctrl/rockchip.h provides defines that map pin numbers to pin names.
Use them to make the dts more human readable.
Change-Id: If1e7f9e9bb108f1fceeb32c9220a20eee7acc01d
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 366812fa2641da395fbf8e7de532c3c463e7b7d2)
This change updates the USB configuration for the RK3399-Q7 in the DTS:
* fixes the OTG board configuration by enabling it ('okay')
* improves the speed of 'usb start' by disabling the unused EHCI/OHCI
controllers
Change-Id: I2ea0f58c8e56ceac065617c8c26007871716273d
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit b1e1ce2cd429c227ef0b2a72b1c13d91ef5555a3)
To correctly model the usbhub_enable regulator for U-Boot, we need
to change the settings to:
* the GPIO polarity is GPIO_ACTIVE_LOW
* should be set to inactive (enable-active-low) when boot-on settings
are applied
* it can be changed at runtime (i.e. remove the always-on)
Change-Id: Ibb1762be5b791870b376d251c53ac6b41b5dbbe4
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit f2a95131685e48bdc05c0abded74ae09701c29d7)
The fixed regulator for overriding BIOS_DISABLE had been modelling
backwards (i.e. the GPIO polarity and the enable-active-low/high
property had both been inverted), causing the 'regulator' command
to always print/expect 'disabled'/'enabled' backwards.
This fixes the mix-up and models it correctly:
* the GPIO is low-active
* the regulator should be enabled (enable-active-high) during
boot-on initialisation
Change-Id: I868f3d9ebaed3d1a17b66244dd84ed9332bf24a1
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit df1e6212f957627731daf9844efe960ca8a549df)
Kever Yang
Jason Zhu
Masahiro Yamada
Prabhakar Kushwaha
Felix Brack
York Sun
Peng Fan
Andre Przywara
Philipp Tomsich
Michal Simek
Stephen Warren
Klaus Goger