CONFIG_ROCKCHIP_UART_MUX_SEL is used for selecting uart multiplexer
in board_debug_uart_init.
Change-Id: I75fb8eab76e4db8cd171d8d6c4462abe52ed168e
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Kernel will alloc reserved memory dynamically for the node.
This patch avoids the sysmem warning dump.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9b3a397c022450c152d479a60877551ee803ef91
Vop WIN with multi-region support(win2 of rv1126)
should enable the bit.
Change-Id: I3e2c4165e0d2c597ab839829f9cbed6a1e37c59a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
In order to prevent physical memory from being written oversize,
limit the decompressed buffer size, user can assign a size to
decompress, the reserved destination buffer size is a choice
Change-Id: I8723c5ec8d58ec1d443c5607987941cf67cf1a01
Signed-off-by: Simon Xue <xxm@rock-chips.com>
1.Logical offset should not mix with map address
2.Format with nand_read_skip_bad
Change-Id: I0e5adec374ce4de437e4ce7368caec4c7c07e83b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Change-Id: I2718843dd4646b7450c36e84cc16e6440c718959
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0)
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.
This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method
Change-Id: I31aec45275decfb03af2829c744c3dda0e261d12
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e365de90517ba4686d7a88417b1a729f5891d376)
This patch handles the issue in SPL:
U-Boot SPL board initspl_early_init()
- found match at 'rv1126_syscon'
- found match at 'rv1126_syscon'
- found match at 'syscon'
- found match at 'rockchip_rv1126_pmucru'
- found match at 'rockchip_rv1126_cru'
- found match at 'ns16550_serial'
- found match at 'rockchip_rk3288_dw_mshc'
- found match at 'rk_nandc_v6'
- found match at 'rockchip_sfc'
- found match at 'spi_nand'
- found match at 'spi_flash_std'
- found match at 'rockchip_crypto_v2'
- found match at 'rockchip_secure_otp_v2'
Cannot find uclass for id 36: please add the UCLASS_DRIVER() declaration for this UCLASS_... id
Missing uclass for driver rockchip_secure_otp_v2
secure_otp@0xff5d0000: ret=-96
dm_scan_fdt() failed: -96
dm_extended_scan_dt() failed: -96
dm_init_and_scan() returned error -96
spl_early_init() failed: -96
......
The root cause is drivers/misc/rockchip-secure-otp-v2.S is pre-compile
but not compile every time, it occupies the UCLASS_MISC id as 36.
There are the same situation for other otp drivers, so let's move it to
the end.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I58a2bec703c2af743d209192fefda6ff6167b01c
This is done by default in the raw NAND core (nand_base.c) but was
missing in the SPI-NAND core. Without these two lines the ecc_strength
and ecc_step_size values are not exported to the user through sysfs.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Change-Id: I37f29616e1522d9ce9e9d7ec18a473c73e1d1551
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
Change-Id: Ieaa72162810105bf5d62caf2efc16a1c2ef89d6d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.
Fix this by explicitly setting req.mode to MTD_OPS_RAW.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
Change-Id: Id415efc0cd8d61d97d98e0340729f8bc60fc28cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.
This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07eedf ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.
To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
Change-Id: I5a47981f004c60d753da382ef6d683a7da1e436b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Linux has good support for Toshiba SPI-NAND, so lets import it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I70a328bf28c7e8740d818958faf749016dd9ca77
(cherry picked from commit 89127104848cea38bac5d40e3d6973fc203e2df6)
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a1c1605dd46ed31fb7ca15c7c26572739f636ec
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ib60f306cb9e8abec9557e92a6d04d76a7071b9ea
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I214b0b2fbe04a139de911435c4abf224264f5495
YouMin Chen
Joseph Chen
Simon Xue
Shunqing Chen
Wyon Bi
Andy Yan
Jon Lin
Jason Zhu
Simon Glass
William Zhang
Robert Marko
Finley Xiao
David Wu