// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3568-power.h>

/ {
	compatible = "rockchip,rk3568";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
		serial8 = &uart8;
		serial9 = &uart9;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};
#if 0
		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
		};
#endif
	};

#if 0
	arm-pmu {
		compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};
#endif

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
	};

	usbdrd30: usbdrd {
		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
			 <&cru ACLK_USB3OTG0>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbdrd_dwc3: dwc3@fcc00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfcc00000 0x0 0x400000>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "otg";
			phys = <&u2phy0_otg>;
			phy-names = "usb2-phy";
			phy_type = "utmi_wide";
			power-domains = <&power RK3568_PD_PIPE>;
			resets = <&cru SRST_USB3OTG0>;
			reset-names = "usb3-otg";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	usbhost30: usbhost {
		compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
			 <&cru ACLK_USB3OTG1>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usbhost_dwc3: dwc3@fd000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xfd000000 0x0 0x400000>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			phys = <&u2phy0_host>;
			phy-names = "usb2-phy";
			phy_type = "utmi_wide";
			power-domains = <&power RK3568_PD_PIPE>;
			resets = <&cru SRST_USB3OTG1>;
			reset-names = "usb3-host";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	gic: interrupt-controller@fd400000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;

		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		its: interrupt-controller@fd440000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0xfd440000 0x0 0x20000>;
		};
	};

	usb_host0_ehci: usb@fd800000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfd800000 0x0 0x40000>;
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>;
		clock-names = "usbhost", "arbiter";
		phys = <&u2phy1_otg>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host0_ohci: usb@fd840000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfd840000 0x0 0x40000>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>;
		clock-names = "usbhost", "arbiter";
		phys = <&u2phy1_otg>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host1_ehci: usb@fd880000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfd880000 0x0 0x40000>;
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>;
		clock-names = "usbhost", "arbiter";
		phys = <&u2phy1_host>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host1_ohci: usb@fd8c0000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfd8c0000 0x0 0x40000>;
		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>;
		clock-names = "usbhost", "arbiter";
		phys = <&u2phy1_host>;
		phy-names = "usb";
		status = "disabled";
	};

	pmugrf: syscon@fdc20000 {
		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfdc20000 0x0 0x10000>;

		pmu_io_domains: io-domains {
			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
			status = "disabled";
		};
	};

	pipegrf: syscon@fdc50000 {
		compatible = "rockchip,rk3568-pipegrf", "syscon";
		reg = <0x0 0xfdc50000 0x0 0x1000>;
	};

	grf: syscon@fdc60000 {
		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfdc60000 0x0 0x10000>;

		io_domains: io-domains {
			compatible = "rockchip,rk3568-io-voltage-domain";
			status = "disabled";
		};
	};

	pipe_phy_grf0: syscon@fdc70000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc70000 0x0 0x1000>;
	};

	pipe_phy_grf1: syscon@fdc80000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc80000 0x0 0x1000>;
	};

	pipe_phy_grf2: syscon@fdc90000 {
		compatible = "rockchip,pipe-phy-grf", "syscon";
		reg = <0x0 0xfdc90000 0x0 0x1000>;
	};

	usb2phy0_grf: syscon@fdca0000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca0000 0x0 0x8000>;
	};

	usb2phy1_grf: syscon@fdca8000 {
		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
		reg = <0x0 0xfdca8000 0x0 0x8000>;
	};

	pmucru: clock-controller@fdd00000 {
		compatible = "rockchip,rk3568-pmucru";
		reg = <0x0 0xfdd00000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cru: clock-controller@fdd20000 {
		compatible = "rockchip,rk3568-cru";
		reg = <0x0 0xfdd20000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&pmucru CLK_RTC_32K>, <&pmucru PLL_PPLL>,
			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
			<&cru PLL_GPLL>, <&cru ARMCLK>,
			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>;
		assigned-clock-rates =
			<32768>, <100000000>,
			<100000000>, <1000000000>,
			<1188000000>, <600000000>,
			<150000000>, <100000000>,
			<300000000>, <200000000>,
			<150000000>, <100000000>,
			<300000000>, <150000000>;
		assigned-clock-parents =
			<&pmucru CLK_RTC32K_FRAC>;
	};

	i2c0: i2c@fdd40000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfdd40000 0x0 0x1000>;
		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart0: serial@fdd50000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfdd50000 0x0 0x100>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 0>, <&dmac0 1>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer>;
		status = "disabled";
	};

	pwm0: pwm@fdd70000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm1: pwm@fdd70010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm2: pwm@fdd70020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2m0_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm3: pwm@fdd70030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfdd70030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3_pins>;
		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pmu: power-management@fdd90000 {
		compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xfdd90000 0x0 0x1000>;

		power: power-controller {
			compatible = "rockchip,rk3568-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			/* These power domains are grouped by VD_NPU */
			pd_npu@RK3568_PD_NPU {
				reg = <RK3568_PD_NPU>;
				pm_qos = <&qos_npu>;
			};
			/* These power domains are grouped by VD_GPU */
			pd_gpu@RK3568_PD_GPU {
				reg = <RK3568_PD_GPU>;
				pm_qos = <&qos_gpu>;
			};
			/* These power domains are grouped by VD_LOGIC */
			pd_vi@RK3568_PD_VI {
				reg = <RK3568_PD_VI>;
				pm_qos = <&qos_isp>,
					 <&qos_vicap0>,
					 <&qos_vicap1>;
			};
			pd_vo@RK3568_PD_VO {
				reg = <RK3568_PD_VO>;
				pm_qos = <&qos_hdcp>,
					 <&qos_vop_m0>,
					 <&qos_vop_m1>;
			};
			pd_rga@RK3568_PD_RGA {
				reg = <RK3568_PD_RGA>;
				pm_qos = <&qos_ebc>,
					 <&qos_iep>,
					 <&qos_jpeg_dec>,
					 <&qos_jpeg_enc>,
					 <&qos_rga_rd>,
					 <&qos_rga_wr>;
			};
			pd_vpu@RK3568_PD_VPU {
				reg = <RK3568_PD_VPU>;
				pm_qos = <&qos_vpu>;
			};
			pd_rkvdec@RK3568_PD_RKVDEC {
				reg = <RK3568_PD_RKVDEC>;
				pm_qos = <&qos_rkvdec>;
			};
			pd_rkvenc@RK3568_PD_RKVENC {
				reg = <RK3568_PD_RKVENC>;
				pm_qos = <&qos_rkvenc_rd_m0>,
					 <&qos_rkvenc_rd_m1>,
					 <&qos_rkvenc_wr_m0>;
			};
			pd_pipe@RK3568_PD_PIPE {
				reg = <RK3568_PD_PIPE>;
				pm_qos = <&qos_pcie2x1>,
					 <&qos_pcie3x1>,
					 <&qos_pcie3x2>,
					 <&qos_sata0>,
					 <&qos_sata1>,
					 <&qos_sata2>,
					 <&qos_usb3_0>,
					 <&qos_usb3_1>;
			};
		};
	};

	gpu: gpu@fde60000 {
		compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
		reg = <0x0 0xfde60000 0x0 0x4000>;

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "GPU", "MMU", "JOB";

		upthreshold = <40>;
		downdifferential = <10>;

		clocks = <&cru CLK_GPU>;
		clock-names = "clk_mali";
		power-domains = <&power RK3568_PD_GPU>;
		#cooling-cells = <2>;
		operating-points-v2 = <&gpu_opp_table>;

		status = "disabled";
		power_model {
			compatible = "arm,mali-simple-power-model";
			static-coefficient = <411000>;
			dynamic-coefficient = <733>;
			ts = <32000 4700 (-80) 2>;
			thermal-zone = "gpu-thermal";
		};
	};

	gpu_opp_table: opp-table2 {
		compatible = "operating-points-v2";

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <1000000>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1000000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <1000000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1000000>;
		};
	};

	qos_gpu: qos@fe128000 {
		compatible = "syscon";
		reg = <0x0 0xfe128000 0x0 0x20>;
	};

	qos_rkvenc_rd_m0: qos@fe138080 {
		compatible = "syscon";
		reg = <0x0 0xfe138080 0x0 0x20>;
	};

	qos_rkvenc_rd_m1: qos@fe138100 {
		compatible = "syscon";
		reg = <0x0 0xfe138100 0x0 0x20>;
	};

	qos_rkvenc_wr_m0: qos@fe138180 {
		compatible = "syscon";
		reg = <0x0 0xfe138180 0x0 0x20>;
	};

	qos_isp: qos@fe148000 {
		compatible = "syscon";
		reg = <0x0 0xfe148000 0x0 0x20>;
	};

	qos_vicap0: qos@fe148080 {
		compatible = "syscon";
		reg = <0x0 0xfe148080 0x0 0x20>;
	};

	qos_vicap1: qos@fe148100 {
		compatible = "syscon";
		reg = <0x0 0xfe148100 0x0 0x20>;
	};

	qos_vpu: qos@fe150000 {
		compatible = "syscon";
		reg = <0x0 0xfe150000 0x0 0x20>;
	};

	qos_ebc: qos@fe158000 {
		compatible = "syscon";
		reg = <0x0 0xfe158000 0x0 0x20>;
	};

	qos_iep: qos@fe158100 {
		compatible = "syscon";
		reg = <0x0 0xfe158100 0x0 0x20>;
	};

	qos_jpeg_dec: qos@fe158180 {
		compatible = "syscon";
		reg = <0x0 0xfe158180 0x0 0x20>;
	};

	qos_jpeg_enc: qos@fe158200 {
		compatible = "syscon";
		reg = <0x0 0xfe158200 0x0 0x20>;
	};

	qos_rga_rd: qos@fe158280 {
		compatible = "syscon";
		reg = <0x0 0xfe158280 0x0 0x20>;
	};

	qos_rga_wr: qos@fe158300 {
		compatible = "syscon";
		reg = <0x0 0xfe158300 0x0 0x20>;
	};

	qos_npu: qos@fe180000 {
		compatible = "syscon";
		reg = <0x0 0xfe180000 0x0 0x20>;
	};

	qos_pcie2x1: qos@fe190000 {
		compatible = "syscon";
		reg = <0x0 0xfe190000 0x0 0x20>;
	};

	qos_pcie3x1: qos@fe190080 {
		compatible = "syscon";
		reg = <0x0 0xfe190080 0x0 0x20>;
	};

	qos_pcie3x2: qos@fe190100 {
		compatible = "syscon";
		reg = <0x0 0xfe190100 0x0 0x20>;
	};

	qos_sata0: qos@fe190200 {
		compatible = "syscon";
		reg = <0x0 0xfe190200 0x0 0x20>;
	};

	qos_sata1: qos@fe190280 {
		compatible = "syscon";
		reg = <0x0 0xfe190280 0x0 0x20>;
	};

	qos_sata2: qos@fe190300 {
		compatible = "syscon";
		reg = <0x0 0xfe190300 0x0 0x20>;
	};

	qos_usb3_0: qos@fe190380 {
		compatible = "syscon";
		reg = <0x0 0xfe190380 0x0 0x20>;
	};

	qos_usb3_1: qos@fe190400 {
		compatible = "syscon";
		reg = <0x0 0xfe190400 0x0 0x20>;
	};

	qos_rkvdec: qos@fe198000 {
		compatible = "syscon";
		reg = <0x0 0xfe198000 0x0 0x20>;
	};

	qos_hdcp: qos@fe1a8000 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8000 0x0 0x20>;
	};

	qos_vop_m0: qos@fe1a8080 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8080 0x0 0x20>;
	};

	qos_vop_m1: qos@fe1a8100 {
		compatible = "syscon";
		reg = <0x0 0xfe1a8100 0x0 0x20>;
	};

	sdmmc2: dwmmc@fe000000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe000000 0x0 0x4000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
			 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC2>;
		reset-names = "reset";
		status = "disabled";
	};

	sdmmc0: dwmmc@fe2b0000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe2b0000 0x0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
			 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC0>;
		reset-names = "reset";
		status = "disabled";
	};

	sdmmc1: dwmmc@fe2c0000 {
		compatible = "rockchip,rk3568-dw-mshc",
			     "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xfe2c0000 0x0 0x4000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <150000000>;
		clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
			 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		resets = <&cru SRST_SDMMC1>;
		reset-names = "reset";
		status = "disabled";
	};

	sfc: sfc@fe300000 {
		compatible = "rockchip,sfc";
		reg = <0x0 0xfe300000 0x0 0x4000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		assigned-clocks = <&cru SCLK_SFC>;
		assigned-clock-rates = <100000000>;
		status = "disabled";
	};

	sdhci: sdhci@fe310000 {
		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
		reg = <0x0 0xfe310000 0x0 0x10000>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru CCLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
		assigned-clock-rates = <200000000>, <200000000>, <24000000>;
		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
			 <&cru TCLK_EMMC>;
		clock-names = "core", "bus", "axi", "block", "timer";
		status = "disabled";
	};

	nandc0: nandc@fe330000 {
		compatible = "rockchip,rk-nandc";
		reg = <0x0 0xfe330000 0x0 0x4000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		nandc_id = <0>;
		clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>;
		clock-names = "clk_nandc", "hclk_nandc";
		status = "disabled";
	};

	i2s0_8ch: i2s@fe400000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe400000 0x0 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 0>;
		dma-names = "tx";
		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		rockchip,playback-only;
		status = "disabled";
	};

	i2s1_8ch: i2s@fe410000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe410000 0x0 0x1000>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 2>, <&dmac1 3>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1sclktxm0
			     &i2s1sclkrxm0
			     &i2s1lrcktxm0
			     &i2s1lrckrxm0
			     &i2s1sdi0m0
			     &i2s1sdi1m0
			     &i2s1sdi2m0
			     &i2s1sdi3m0
			     &i2s1sdo0m0
			     &i2s1sdo1m0
			     &i2s1sdo2m0
			     &i2s1sdo3m0>;
		status = "disabled";
	};

	i2s2_2ch: i2s@fe420000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe420000 0x0 0x1000>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 4>, <&dmac1 5>;
		dma-names = "tx", "rx";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		rockchip,clk-trcm = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2sclktxm0
			     &i2s2lrcktxm0
			     &i2s2sdim0
			     &i2s2sdom0>;
		status = "disabled";
	};

	i2s3_2ch: i2s@fe430000 {
		compatible = "rockchip,rk3568-i2s-tdm";
		reg = <0x0 0xfe430000 0x0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac1 6>, <&dmac1 7>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s3sclkm0
			     &i2s3lrckm0
			     &i2s3sdim0
			     &i2s3sdom0>;
		status = "disabled";
	};

	pdm: pdm@fe440000 {
		compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
		reg = <0x0 0xfe440000 0x0 0x1000>;
		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
		clock-names = "pdm_clk", "pdm_hclk";
		dmas = <&dmac1 9>;
		dma-names = "rx";
		status = "disabled";
	};

	spdif_8ch: spdif@fe460000 {
		compatible = "rockchip,rk3588-spdif";
		reg = <0x0 0xfe460000 0x0 0x1000>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&dmac1 1>;
		dma-names = "tx";
		clock-names = "mclk", "hclk";
		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdifm0_pins>;
		status = "disabled";
	};

	audpwm: audpwm@fe470000 {
		compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1";
		reg = <0x0 0xfe470000 0x0 0x1000>;
		clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
		clock-names = "clk", "hclk";
		dmas = <&dmac1 8>;
		dma-names = "tx";
		rockchip,sample-width-bits = <11>;
		rockchip,interpolat-points = <1>;
		status = "disabled";
	};

	dig_acodec: codec-digital@fe478000 {
		compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1";
		reg = <0x0 0xfe478000 0x0 0x1000>;
		clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, <&cru HCLK_ACDCDIG>;
		clock-names = "adc", "dac", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&acodec_pins>;
		resets = <&cru SRST_ACDCDIG>;
		reset-names = "reset" ;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	dmac0: dmac@fe530000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfe530000 0x0 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DMAC0>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		arm,pl330-periph-burst;
	};

	dmac1: dmac@fe550000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0xfe550000 0x0 0x4000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DMAC1>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		arm,pl330-periph-burst;
	};

	can0: can@fe570000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe570000 0x0 0x1000>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	can1: can@fe580000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe580000 0x0 0x1000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	can2: can@fe590000 {
		compatible = "rockchip,canfd-1.0";
		reg = <0x0 0xfe590000 0x0 0x1000>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
		reset-names = "can", "can-apb";
		tx-fifo-depth = <1>;
		rx-fifo-depth = <6>;
		status = "disabled";
	};

	i2c1: i2c@fe5a0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5a0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@fe5b0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5b0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@fe5c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5c0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@fe5d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5d0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c5: i2c@fe5e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xfe5e0000 0x0 0x1000>;
		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	wdt: watchdog@fe600000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0xfe600000 0x0 0x100>;
		clocks = <&cru PCLK_WDT_NS>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		status = "okay";
	};

	spi0: spi@fe610000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe610000 0x0 0x1000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 20>, <&dmac0 21>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0clkm0 &spi0cs0m0 &spi0cs1m0 &spi0misom0 &spi0mosim0>;
		status = "disabled";
	};

	spi1: spi@fe620000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe620000 0x0 0x1000>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 22>, <&dmac0 23>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi1clkm0 &spi1cs0m0 &spi1cs1m0 &spi1misom0 &spi1mosim0>;
		status = "disabled";
	};

	spi2: spi@fe630000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe630000 0x0 0x1000>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 24>, <&dmac0 25>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi2clkm0 &spi2cs0m0 &spi2cs1m0 &spi2misom0 &spi2mosim0>;
		status = "disabled";
	};

	spi3: spi@fe640000 {
		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xfe640000 0x0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac0 26>, <&dmac0 27>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi3clkm0 &spi3cs0m0 &spi3cs1m0 &spi3misom0 &spi3mosim0>;
		status = "disabled";
	};

	uart1: serial@fe650000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe650000 0x0 0x100>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 2>, <&dmac0 3>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1m0_xfer>;
		status = "disabled";
	};

	uart2: serial@fe660000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe660000 0x0 0x100>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 4>, <&dmac0 5>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m0_xfer>;
		status = "disabled";
	};

	uart3: serial@fe670000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe670000 0x0 0x100>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 6>, <&dmac0 7>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart3m0_xfer>;
		status = "disabled";
	};

	uart4: serial@fe680000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe680000 0x0 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 8>, <&dmac0 9>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart4m0_xfer>;
		status = "disabled";
	};

	uart5: serial@fe690000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe690000 0x0 0x100>;
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 10>, <&dmac0 11>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart5m0_xfer>;
		status = "disabled";
	};

	uart6: serial@fe6a0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6a0000 0x0 0x100>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 12>, <&dmac0 13>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart6m0_xfer>;
		status = "disabled";
	};

	uart7: serial@fe6b0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6b0000 0x0 0x100>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 14>, <&dmac0 15>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart7m0_xfer>;
		status = "disabled";
	};

	uart8: serial@fe6c0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6c0000 0x0 0x100>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 16>, <&dmac0 17>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart8m0_xfer>;
		status = "disabled";
	};

	uart9: serial@fe6d0000 {
		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
		reg = <0x0 0xfe6d0000 0x0 0x100>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac0 18>, <&dmac0 19>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart9m0_xfer>;
		status = "disabled";
	};

	pwm4: pwm@fe6e0000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm4_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm5: pwm@fe6e0010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm5_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm6: pwm@fe6e0020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm6_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm7: pwm@fe6e0030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6e0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm7_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm8: pwm@fe6f0000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm8m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm9: pwm@fe6f0010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm9m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm10: pwm@fe6f0020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm10m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm11: pwm@fe6f0030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe6f0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm11m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm12: pwm@fe700000 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm12m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm13: pwm@fe700010 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm13m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm14: pwm@fe700020 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm14m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm15: pwm@fe700030 {
		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xfe700030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm15m0_pins>;
		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	saradc: saradc@fe720000 {
		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
		reg = <0x0 0xfe720000 0x0 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_P_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	combphy0_us: phy@fe820000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe820000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
		clock-names = "refclk", "apbclk";
		resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
		status = "disabled";
	};

	combphy1_usq: phy@fe830000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe830000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>;
		clock-names = "refclk", "apbclk";
		resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
		status = "disabled";
	};

	combphy2_psq: phy@fe840000 {
		compatible = "rockchip,rk3568-naneng-combphy";
		reg = <0x0 0xfe840000 0x0 0x100>;
		#phy-cells = <1>;
		clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>;
		clock-names = "refclk", "apbclk";
		resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
		reset-names = "combphy-apb", "combphy";
		rockchip,pipe-grf = <&pipegrf>;
		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
		status = "disabled";
	};

	usb2phy0: usb2-phy@fe8a0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY0_REF>;
		clock-names = "phyclk";
		#clock-cells = <0>;
		clock-output-names = "usb480m_phy";
		rockchip,usbgrf = <&usb2phy0_grf>;
		status = "disabled";

		u2phy0_host: host-port {
		#phy-cells = <0>;
		status = "disabled";
		};

		u2phy0_otg: otg-port {
		#phy-cells = <0>;
		status = "disabled";
		};
	};

	usb2phy1: usb2-phy@fe8b0000 {
		compatible = "rockchip,rk3568-usb2phy";
		reg = <0x0 0xfe8b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pmucru CLK_USBPHY1_REF>;
		clock-names = "phyclk";
		rockchip,usbgrf = <&usb2phy1_grf>;
		status = "disabled";

		u2phy1_host: host-port {
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy1_otg: otg-port {
			#phy-cells = <0>;
			status = "disabled";
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3568-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio@fdd60000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfdd60000 0x0 0x100>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@fe740000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe740000 0x0 0x100>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 32 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@fe750000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe750000 0x0 0x100>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 64 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@fe760000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe750000 0x0 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 96 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@fe770000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xfe770000 0x0 0x100>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 128 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "rk3568-pinctrl.dtsi"