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Chin Liang See 5405817a6e spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value 
Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.

Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
 		2016-08-07 21:54:21 +02:00
..
Kconfig spi: pic32_spi: add SPI master driver for PIC32 SoC. 2016-06-10 12:31:12 +02:00
Makefile spi: pic32_spi: add SPI master driver for PIC32 SoC. 2016-06-10 12:31:12 +02:00
altera_spi.c
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armada100_spi.c
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ath79_spi.c ath79: spi: Remove the explicit pinctrl setting 2016-05-21 01:36:37 +02:00
atmel_dataflash_spi.c
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atmel_spi.c
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atmel_spi.h
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bfin_spi.c
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bfin_spi6xx.c
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cadence_qspi.c spi: cadence_quadspi: Enable QUAD mode based on DT data 2016-07-09 20:16:33 +05:30
cadence_qspi.h spi: cadence_quadspi: Enable QUAD mode based on DT data 2016-07-09 20:16:33 +05:30
cadence_qspi_apb.c spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value 2016-08-07 21:54:21 +02:00
cf_qspi.c
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cf_spi.c
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davinci_spi.c spi: davinci_spi: Convert to driver to adapt to DM 2016-07-09 20:16:30 +05:30
designware_spi.c
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ep93xx_spi.c
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exynos_spi.c
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fsl_dspi.c
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fsl_espi.c
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fsl_qspi.c driver: spi: fsl-qspi: remove compile Warnings 2016-08-02 09:45:13 -07:00
fsl_qspi.h
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ich.c dm: pch: Rename get_sbase op to get_spi_base 2016-02-05 12:47:21 +08:00
ich.h spi: ich: Change PCHV_ to ICHV_ 2016-02-05 12:47:20 +08:00
kirkwood_spi.c spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU 2016-04-06 15:38:56 +02:00
lpc32xx_ssp.c
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mpc8xxx_spi.c
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mpc52xx_spi.c
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mxc_spi.c
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mxs_spi.c
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omap3_spi.c omap3: Fix SPI registers on am33xx and am43xx 2016-05-23 11:50:22 -04:00
pic32_spi.c spi: pic32_spi: add SPI master driver for PIC32 SoC. 2016-06-10 12:31:12 +02:00
rk_spi.c clk: convert API to match reset/mailbox style 2016-06-19 17:05:55 -06:00
rk_spi.h
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sandbox_spi.c
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sh_qspi.c
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sh_spi.c Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
sh_spi.h Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
soft_spi.c dm: spi: soft_spi: switch to use linux compatible string 2016-05-17 09:54:43 -06:00
soft_spi_legacy.c
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spi-emul-uclass.c
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spi-uclass.c dm: Use dm_scan_fdt_dev() directly where possible 2016-07-27 14:15:54 -06:00
spi.c
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tegra20_sflash.c
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tegra20_slink.c Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
tegra114_spi.c Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
tegra210_qspi.c
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tegra_spi.h
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ti_qspi.c spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock 2016-07-30 00:15:00 +05:30
xilinx_spi.c
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zynq_qspi.c
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zynq_spi.c
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