York Sun 9955b4ab01 driver/ddr/fsl: Add workaround for A008336 ... Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>		2015-02-24 13:09:06 -08:00
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fsl	driver/ddr/fsl: Add workaround for A008336	2015-02-24 13:09:06 -08:00
mvebu	arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr	2015-02-06 17:25:03 +01:00