ab86434d69
Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Change-Id: Iee0b8cb304816d74c6442132be4cc04e6cb8adbc Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit df16881cea50a787c37591bd2168c8ea656217bd) |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nds32 | ||
| nios2 | ||
| powerpc | ||
| sandbox | ||
| sh | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||