933 lines
21 KiB
C
933 lines
21 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <amp.h>
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#include <android_bootloader.h>
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#include <android_image.h>
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#include <bidram.h>
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#include <boot_rkimg.h>
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#include <cli.h>
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#include <clk.h>
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#include <console.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <dvfs.h>
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#include <io-domain.h>
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#include <image.h>
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#include <key.h>
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#include <memblk.h>
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#include <misc.h>
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#include <of_live.h>
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#include <mtd_blk.h>
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#include <ram.h>
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#include <rockchip_debugger.h>
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#include <syscon.h>
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#include <sysmem.h>
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#include <video_rockchip.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dm/uclass-internal.h>
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#include <dm/root.h>
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#include <power/charge_display.h>
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#include <power/regulator.h>
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#include <optee_include/OpteeClientInterface.h>
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#include <optee_include/OpteeClientApiLib.h>
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#include <optee_include/tee_api_defines.h>
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#include <asm/arch/boot_mode.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hotkey.h>
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#include <asm/arch/param.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/resource_img.h>
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#include <asm/arch/rk_atags.h>
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#include <asm/arch/vendor.h>
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#ifdef CONFIG_ROCKCHIP_EINK_DISPLAY
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#include <rk_eink.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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__weak int rk_board_fdt_fixup(void *blob)
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{
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return 0;
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}
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__weak int soc_clk_dump(void)
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{
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return 0;
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}
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__weak int set_armclk_rate(void)
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{
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return 0;
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}
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__weak int rk_board_init(void)
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{
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return 0;
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}
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/*
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* define serialno max length, the max length is 512 Bytes
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* The remaining bytes are used to ensure that the first 512 bytes
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* are valid when executing 'env_set("serial#", value)'.
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*/
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#define VENDOR_SN_MAX 513
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#define CPUID_LEN 0x10
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#define CPUID_OFF 0x07
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#define MAX_ETHERNET 0x2
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static int rockchip_set_ethaddr(void)
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{
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#ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
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char buf[ARP_HLEN_ASCII + 1], mac[16];
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u8 ethaddr[ARP_HLEN * MAX_ETHERNET] = {0};
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int ret, i;
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bool need_write = false, randomed = false;
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ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr));
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for (i = 0; i < MAX_ETHERNET; i++) {
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if (ret <= 0 || !is_valid_ethaddr(ðaddr[i * ARP_HLEN])) {
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if (!randomed) {
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net_random_ethaddr(ðaddr[i * ARP_HLEN]);
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randomed = true;
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} else {
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if (i > 0) {
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memcpy(ðaddr[i * ARP_HLEN],
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ðaddr[(i - 1) * ARP_HLEN],
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ARP_HLEN);
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ethaddr[i * ARP_HLEN] |= 0x02;
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ethaddr[i * ARP_HLEN] += (i << 2);
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}
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}
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need_write = true;
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}
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if (is_valid_ethaddr(ðaddr[i * ARP_HLEN])) {
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sprintf(buf, "%pM", ðaddr[i * ARP_HLEN]);
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if (i == 0)
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memcpy(mac, "ethaddr", sizeof("ethaddr"));
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else
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sprintf(mac, "eth%daddr", i);
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env_set(mac, buf);
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}
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}
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if (need_write) {
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ret = vendor_storage_write(VENDOR_LAN_MAC_ID,
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ethaddr, sizeof(ethaddr));
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if (ret < 0)
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printf("%s: vendor_storage_write failed %d\n",
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__func__, ret);
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}
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#endif
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return 0;
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}
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static int rockchip_set_serialno(void)
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{
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u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2];
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u8 cpuid[CPUID_LEN] = {0};
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char serialno_str[VENDOR_SN_MAX];
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int ret = 0, i;
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u64 serialno;
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/* Read serial number from vendor storage part */
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memset(serialno_str, 0, VENDOR_SN_MAX);
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#ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
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ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1));
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if (ret > 0) {
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i = strlen(serialno_str);
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for (; i > 0; i--) {
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if ((serialno_str[i] >= 'a' && serialno_str[i] <= 'z') ||
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(serialno_str[i] >= 'A' && serialno_str[i] <= 'Z') ||
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(serialno_str[i] >= '0' && serialno_str[i] <= '9'))
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break;
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}
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serialno_str[i + 1] = 0x0;
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env_set("serial#", serialno_str);
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} else {
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#endif
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#if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
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struct udevice *dev;
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/* retrieve the device */
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if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(rockchip_efuse),
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&dev);
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else
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(rockchip_otp),
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&dev);
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if (ret) {
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printf("%s: could not find efuse/otp device\n", __func__);
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return ret;
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}
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/* read the cpu_id range from the efuses */
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ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid));
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if (ret) {
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printf("%s: read cpuid from efuse/otp failed, ret=%d\n",
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__func__, ret);
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return ret;
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}
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#else
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/* generate random cpuid */
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for (i = 0; i < CPUID_LEN; i++)
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cpuid[i] = (u8)(rand());
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#endif
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/* Generate the serial number based on CPU ID */
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for (i = 0; i < 8; i++) {
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low[i] = cpuid[1 + (i << 1)];
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high[i] = cpuid[i << 1];
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}
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serialno = crc32_no_comp(0, low, 8);
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serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
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snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
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env_set("serial#", serialno_str);
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#ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
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}
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#endif
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return ret;
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}
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#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
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int fb_set_reboot_flag(void)
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{
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printf("Setting reboot to fastboot flag ...\n");
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writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
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return 0;
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}
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#endif
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#ifdef CONFIG_ROCKCHIP_USB_BOOT
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static int boot_from_udisk(void)
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{
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struct blk_desc *desc;
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char *devtype;
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char *devnum;
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devtype = env_get("devtype");
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devnum = env_get("devnum");
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/* Booting priority: mmc1 > udisk */
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if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1"))
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return 0;
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if (!run_command("usb start", -1)) {
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desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
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if (!desc) {
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printf("No usb device found\n");
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return -ENODEV;
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}
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if (!run_command("rkimgtest usb 0", -1)) {
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rockchip_set_bootdev(desc);
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env_set("devtype", "usb");
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env_set("devnum", "0");
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printf("Boot from usb 0\n");
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} else {
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printf("No usb dev 0 found\n");
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return -ENODEV;
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}
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}
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return 0;
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}
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#endif
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static void env_fixup(void)
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{
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struct memblock mem;
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ulong u_addr_r;
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phys_size_t end;
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char *addr_r;
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#ifdef ENV_MEM_LAYOUT_SETTINGS1
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const char *env_addr0[] = {
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"scriptaddr", "pxefile_addr_r",
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"fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r",
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};
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const char *env_addr1[] = {
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"scriptaddr1", "pxefile_addr1_r",
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"fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r",
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};
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int i;
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/* 128M is a typical ram size for most platform, so as default here */
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if (gd->ram_size <= SZ_128M) {
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/* Replace orignal xxx_addr_r */
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for (i = 0; i < ARRAY_SIZE(env_addr1); i++) {
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addr_r = env_get(env_addr1[i]);
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if (addr_r)
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env_set(env_addr0[i], addr_r);
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}
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}
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#endif
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/* If BL32 is disabled, move kernel to lower address. */
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if (!(gd->flags & GD_FLG_BL32_ENABLED)) {
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addr_r = env_get("kernel_addr_no_bl32_r");
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if (addr_r)
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env_set("kernel_addr_r", addr_r);
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/*
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* 0x0a200000 and 0x08400000 are rockchip traditional address
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* of BL32 and ramdisk:
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*
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* |------------|------------|
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* | BL32 | ramdisk |
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* |------------|------------|
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*
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* Move ramdisk to BL32 address to fix sysmem alloc failed
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* issue on the board with critical memory(ie. 256MB).
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*/
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if (gd->ram_size > SZ_128M && gd->ram_size <= SZ_256M) {
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u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0);
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if (u_addr_r == 0x0a200000)
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env_set("ramdisk_addr_r", "0x08400000");
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}
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/* If BL32 is enlarged, move ramdisk right behind it */
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} else {
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mem = param_parse_optee_mem();
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end = mem.base + mem.size;
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u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0);
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if (u_addr_r >= mem.base && u_addr_r < end)
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env_set_hex("ramdisk_addr_r", end);
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}
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}
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static void cmdline_handle(void)
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{
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#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
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struct tag *t;
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t = atags_get_tag(ATAG_PUB_KEY);
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if (t) {
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/* Pass if efuse/otp programmed */
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if (t->u.pub_key.flag == PUBKEY_FUSE_PROGRAMMED)
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env_update("bootargs", "fuse.programmed=1");
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else
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env_update("bootargs", "fuse.programmed=0");
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}
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#endif
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}
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int board_late_init(void)
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{
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rockchip_set_ethaddr();
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rockchip_set_serialno();
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setup_download_mode();
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#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
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setup_boot_mode();
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#endif
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#ifdef CONFIG_ROCKCHIP_USB_BOOT
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boot_from_udisk();
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#endif
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#ifdef CONFIG_DM_CHARGE_DISPLAY
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charge_display();
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#endif
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#ifdef CONFIG_DRM_ROCKCHIP
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rockchip_show_logo();
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#endif
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#ifdef CONFIG_ROCKCHIP_EINK_DISPLAY
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rockchip_eink_show_uboot_logo();
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#endif
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env_fixup();
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soc_clk_dump();
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cmdline_handle();
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return rk_board_late_init();
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}
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static void early_download(void)
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{
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#if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \
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(CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0)
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if (pwrkey_download_init())
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printf("Pwrkey download init failed\n");
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#endif
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#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
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if (is_hotkey(HK_BROM_DNL)) {
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printf("Enter bootrom download...");
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flushc();
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writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
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do_reset(NULL, 0, 0, NULL);
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printf("failed!\n");
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}
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#endif
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}
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static void board_debug_init(void)
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{
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if (!gd->serial.using_pre_serial &&
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!(gd->flags & GD_FLG_DISABLE_CONSOLE))
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debug_uart_init();
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if (tstc()) {
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gd->console_evt = getc();
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if (gd->console_evt <= 0x1a) /* 'z' */
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printf("Hotkey: ctrl+%c\n", gd->console_evt + 'a' - 1);
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}
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if (IS_ENABLED(CONFIG_CONSOLE_DISABLE_CLI))
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printf("Cmd interface: disabled\n");
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}
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#ifdef CONFIG_MTD_BLK
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static void board_mtd_blk_map_partitions(void)
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{
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struct blk_desc *dev_desc;
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dev_desc = rockchip_get_bootdev();
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if (dev_desc)
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mtd_blk_map_partitions(dev_desc);
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}
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#endif
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int board_init(void)
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{
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board_debug_init();
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#ifdef DEBUG
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soc_clk_dump();
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#endif
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#ifdef CONFIG_USING_KERNEL_DTB
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#ifdef CONFIG_MTD_BLK
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board_mtd_blk_map_partitions();
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#endif
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init_kernel_dtb();
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#endif
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early_download();
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/*
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* pmucru isn't referenced on some platforms, so pmucru driver can't
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* probe that the "assigned-clocks" is unused.
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*/
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clks_probe();
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#ifdef CONFIG_DM_REGULATOR
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if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR)))
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debug("%s: Can't enable boot on regulator\n", __func__);
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#endif
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#ifdef CONFIG_ROCKCHIP_IO_DOMAIN
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io_domain_init();
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#endif
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set_armclk_rate();
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#ifdef CONFIG_DM_DVFS
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dvfs_init(true);
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#endif
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return rk_board_init();
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}
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int interrupt_debugger_init(void)
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{
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#ifdef CONFIG_ROCKCHIP_DEBUGGER
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return rockchip_debugger_init();
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#else
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return 0;
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#endif
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}
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int board_fdt_fixup(void *blob)
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{
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/* Common fixup for DRM */
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#ifdef CONFIG_DRM_ROCKCHIP
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rockchip_display_fixup(blob);
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#endif
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return rk_board_fdt_fixup(blob);
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}
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#if defined(CONFIG_ARM64_BOOT_AARCH32) || !defined(CONFIG_ARM64)
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/*
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* Common for OP-TEE:
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* 64-bit & 32-bit mode: share memory dcache is always enabled;
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*
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* Common for U-Boot:
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* 64-bit mode: MMU table is static defined in rkxxx.c file, all memory
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* regions are mapped. That's good to match OP-TEE MMU policy.
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*
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* 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where
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* the OP-TEE region has been reserved, so it can not be
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* mapped(i.e. dcache is disabled). That's *NOT* good to match
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* OP-TEE MMU policy.
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*
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* For the data coherence when communication between U-Boot and OP-TEE, U-Boot
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* should follow OP-TEE MMU policy.
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*
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* So 32-bit mode U-Boot should map OP-TEE share memory as dcache enabled.
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*/
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int board_initr_caches_fixup(void)
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{
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#ifdef CONFIG_OPTEE_CLIENT
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struct memblock mem;
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mem.base = 0;
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mem.size = 0;
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optee_get_shm_config(&mem.base, &mem.size);
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if (mem.size)
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mmu_set_region_dcache_behaviour(mem.base, mem.size,
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DCACHE_WRITEBACK);
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#endif
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return 0;
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}
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#endif
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void arch_preboot_os(uint32_t bootm_state)
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{
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if (bootm_state & BOOTM_STATE_OS_PREP)
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hotkey_run(HK_CLI_OS_PRE);
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}
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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|
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#ifdef CONFIG_LMB
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/*
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* Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
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* This makes lmb_alloc_base() always alloc from tail of sdram.
|
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* If we don't assign it, bi_dram[0] is used by default and it may cause
|
|
* lmb_alloc_base() fail when bi_dram[0] range is small.
|
|
*/
|
|
void board_lmb_reserve(struct lmb *lmb)
|
|
{
|
|
char bootm_mapsize[32];
|
|
char bootm_low[32];
|
|
u64 start, size;
|
|
int i;
|
|
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
if (!gd->bd->bi_dram[i].size)
|
|
break;
|
|
}
|
|
|
|
start = gd->bd->bi_dram[i - 1].start;
|
|
size = gd->bd->bi_dram[i - 1].size;
|
|
|
|
/*
|
|
* 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+),
|
|
* otherwise "Unable to handle kernel paging request at virtual address ...".
|
|
*
|
|
* So that we hope limit highest address at 768M, but there comes the the
|
|
* problem: ramdisk is a compressed image and it expands after descompress,
|
|
* so it accesses 768MB+ and brings the above "Unable to handle kernel ...".
|
|
*
|
|
* We make a appointment that the highest memory address is 512MB, it
|
|
* makes lmb alloc safer.
|
|
*/
|
|
#ifndef CONFIG_ARM64
|
|
if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) {
|
|
start = gd->bd->bi_dram[i - 2].start;
|
|
size = gd->bd->bi_dram[i - 2].size;
|
|
}
|
|
|
|
if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M))
|
|
size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start;
|
|
#endif
|
|
sprintf(bootm_low, "0x%llx", start);
|
|
sprintf(bootm_mapsize, "0x%llx", size);
|
|
env_set("bootm_low", bootm_low);
|
|
env_set("bootm_mapsize", bootm_mapsize);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_BIDRAM
|
|
int board_bidram_reserve(struct bidram *bidram)
|
|
{
|
|
struct memblock mem;
|
|
int ret;
|
|
|
|
/* ATF */
|
|
mem = param_parse_atf_mem();
|
|
ret = bidram_reserve(MEM_ATF, mem.base, mem.size);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* PSTORE/ATAGS/SHM */
|
|
mem = param_parse_common_resv_mem();
|
|
ret = bidram_reserve(MEM_SHM, mem.base, mem.size);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* OP-TEE */
|
|
mem = param_parse_optee_mem();
|
|
ret = bidram_reserve(MEM_OPTEE, mem.base, mem.size);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
parse_fn_t board_bidram_parse_fn(void)
|
|
{
|
|
return param_parse_ddr_mem;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ROCKCHIP_AMP
|
|
void cpu_secondary_init_r(void)
|
|
{
|
|
amp_cpus_on();
|
|
}
|
|
#endif
|
|
|
|
int board_init_f_boot_flags(void)
|
|
{
|
|
int boot_flags = 0;
|
|
|
|
/* pre-loader serial */
|
|
#if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
|
|
defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
|
|
struct tag *t;
|
|
|
|
t = atags_get_tag(ATAG_SERIAL);
|
|
if (t) {
|
|
gd->serial.using_pre_serial = 1;
|
|
gd->serial.enable = t->u.serial.enable;
|
|
gd->serial.baudrate = t->u.serial.baudrate;
|
|
gd->serial.addr = t->u.serial.addr;
|
|
gd->serial.id = t->u.serial.id;
|
|
gd->baudrate = CONFIG_BAUDRATE;
|
|
if (!t->u.serial.enable)
|
|
boot_flags |= GD_FLG_DISABLE_CONSOLE;
|
|
debug("preloader: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n",
|
|
gd->serial.enable, gd->serial.addr,
|
|
gd->serial.baudrate, gd->serial.id);
|
|
} else
|
|
#endif
|
|
{
|
|
gd->baudrate = CONFIG_BAUDRATE;
|
|
gd->serial.baudrate = CONFIG_BAUDRATE;
|
|
gd->serial.addr = CONFIG_DEBUG_UART_BASE;
|
|
}
|
|
|
|
/* The highest priority to turn off (override) console */
|
|
#if defined(CONFIG_DISABLE_CONSOLE)
|
|
boot_flags |= GD_FLG_DISABLE_CONSOLE;
|
|
#endif
|
|
|
|
return boot_flags;
|
|
}
|
|
|
|
#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
|
|
#include <fdt_support.h>
|
|
#include <usb.h>
|
|
#include <usb/dwc2_udc.h>
|
|
|
|
static struct dwc2_plat_otg_data otg_data = {
|
|
.rx_fifo_sz = 512,
|
|
.np_tx_fifo_sz = 16,
|
|
.tx_fifo_sz = 128,
|
|
};
|
|
|
|
int board_usb_init(int index, enum usb_init_type init)
|
|
{
|
|
const void *blob = gd->fdt_blob;
|
|
const fdt32_t *reg;
|
|
fdt_addr_t addr;
|
|
int node;
|
|
|
|
/* find the usb_otg node */
|
|
node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
|
|
|
|
retry:
|
|
if (node > 0) {
|
|
reg = fdt_getprop(blob, node, "reg", NULL);
|
|
if (!reg)
|
|
return -EINVAL;
|
|
|
|
addr = fdt_translate_address(blob, node, reg);
|
|
if (addr == OF_BAD_ADDR) {
|
|
pr_err("Not found usb_otg address\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
#if defined(CONFIG_ROCKCHIP_RK3288)
|
|
if (addr != 0xff580000) {
|
|
node = fdt_node_offset_by_compatible(blob, node,
|
|
"snps,dwc2");
|
|
goto retry;
|
|
}
|
|
#endif
|
|
} else {
|
|
/*
|
|
* With kernel dtb support, rk3288 dwc2 otg node
|
|
* use the rockchip legacy dwc2 driver "dwc_otg_310"
|
|
* with the compatible "rockchip,rk3288_usb20_otg",
|
|
* and rk3368 also use the "dwc_otg_310" driver with
|
|
* the compatible "rockchip,rk3368-usb".
|
|
*/
|
|
#if defined(CONFIG_ROCKCHIP_RK3288)
|
|
node = fdt_node_offset_by_compatible(blob, -1,
|
|
"rockchip,rk3288_usb20_otg");
|
|
#elif defined(CONFIG_ROCKCHIP_RK3368)
|
|
node = fdt_node_offset_by_compatible(blob, -1,
|
|
"rockchip,rk3368-usb");
|
|
#endif
|
|
if (node > 0) {
|
|
goto retry;
|
|
} else {
|
|
pr_err("Not found usb_otg device\n");
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
otg_data.regs_otg = (uintptr_t)addr;
|
|
|
|
return dwc2_udc_probe(&otg_data);
|
|
}
|
|
|
|
int board_usb_cleanup(int index, enum usb_init_type init)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void bootm_no_reloc(void)
|
|
{
|
|
char *ramdisk_high;
|
|
char *fdt_high;
|
|
|
|
if (!env_get_yesno("bootm-no-reloc"))
|
|
return;
|
|
|
|
ramdisk_high = env_get("initrd_high");
|
|
fdt_high = env_get("fdt_high");
|
|
|
|
if (!fdt_high) {
|
|
env_set_hex("fdt_high", -1UL);
|
|
printf("Fdt ");
|
|
}
|
|
|
|
if (!ramdisk_high) {
|
|
env_set_hex("initrd_high", -1UL);
|
|
printf("Ramdisk ");
|
|
}
|
|
|
|
if (!fdt_high || !ramdisk_high)
|
|
printf("skip relocation\n");
|
|
}
|
|
|
|
int bootm_board_start(void)
|
|
{
|
|
/*
|
|
* print console record data
|
|
*
|
|
* On some rockchip platforms, uart debug and sdmmc pin are multiplex.
|
|
* If boot from sdmmc mode, the console data would be record in buffer,
|
|
* we switch to uart debug function in order to print it after loading
|
|
* images.
|
|
*/
|
|
#if defined(CONFIG_CONSOLE_RECORD)
|
|
if (!strcmp("mmc", env_get("devtype")) &&
|
|
!strcmp("1", env_get("devnum"))) {
|
|
printf("IOMUX: sdmmc => uart debug");
|
|
pinctrl_select_state(gd->cur_serial_dev, "default");
|
|
console_record_print_purge();
|
|
}
|
|
#endif
|
|
/* disable bootm relcation to save boot time */
|
|
bootm_no_reloc();
|
|
|
|
/* sysmem */
|
|
hotkey_run(HK_SYSMEM);
|
|
sysmem_overflow_check();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Implement it to support CLI command:
|
|
* - Android: bootm [aosp addr]
|
|
* - FIT: bootm [fit addr]
|
|
* - uImage: bootm [uimage addr]
|
|
*
|
|
* Purpose:
|
|
* - The original bootm command args require fdt addr on AOSP,
|
|
* which is not flexible on rockchip boot/recovery.img.
|
|
* - Take Android/FIT/uImage image into sysmem management to avoid image
|
|
* memory overlap.
|
|
*/
|
|
#if defined(CONFIG_ANDROID_BOOTLOADER) || \
|
|
defined(CONFIG_ROCKCHIP_FIT_IMAGE) || \
|
|
defined(CONFIG_ROCKCHIP_UIMAGE)
|
|
int board_do_bootm(int argc, char * const argv[])
|
|
{
|
|
int format;
|
|
void *img;
|
|
|
|
if (argc != 2)
|
|
return 0;
|
|
|
|
img = (void *)simple_strtoul(argv[1], NULL, 16);
|
|
format = (genimg_get_format(img));
|
|
|
|
/* Android */
|
|
#ifdef CONFIG_ANDROID_BOOT_IMAGE
|
|
if (format == IMAGE_FORMAT_ANDROID) {
|
|
struct andr_img_hdr *hdr;
|
|
ulong load_addr;
|
|
ulong size;
|
|
int ret;
|
|
|
|
hdr = (struct andr_img_hdr *)img;
|
|
printf("BOOTM: transferring to board Android\n");
|
|
|
|
#ifdef CONFIG_USING_KERNEL_DTB
|
|
sysmem_free((phys_addr_t)gd->fdt_blob);
|
|
/* erase magic */
|
|
fdt_set_magic((void *)gd->fdt_blob, ~0);
|
|
gd->fdt_blob = NULL;
|
|
#endif
|
|
load_addr = env_get_ulong("kernel_addr_r", 16, 0);
|
|
load_addr -= hdr->page_size;
|
|
size = android_image_get_end(hdr) - (ulong)hdr;
|
|
|
|
if (!sysmem_alloc_base(MEM_ANDROID, (ulong)hdr, size))
|
|
return -ENOMEM;
|
|
|
|
ret = android_image_memcpy_separate(hdr, &load_addr);
|
|
if (ret) {
|
|
printf("board do bootm failed, ret=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return android_bootloader_boot_kernel(load_addr);
|
|
}
|
|
#endif
|
|
|
|
/* FIT */
|
|
#if IMAGE_ENABLE_FIT
|
|
if (format == IMAGE_FORMAT_FIT) {
|
|
char boot_cmd[64];
|
|
|
|
printf("BOOTM: transferring to board FIT\n");
|
|
snprintf(boot_cmd, sizeof(boot_cmd), "boot_fit %s", argv[1]);
|
|
return run_command(boot_cmd, 0);
|
|
}
|
|
#endif
|
|
|
|
/* uImage */
|
|
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
|
|
if (format == IMAGE_FORMAT_LEGACY &&
|
|
image_get_type(img) == IH_TYPE_MULTI) {
|
|
char boot_cmd[64];
|
|
|
|
printf("BOOTM: transferring to board uImage\n");
|
|
snprintf(boot_cmd, sizeof(boot_cmd), "boot_uimage %s", argv[1]);
|
|
return run_command(boot_cmd, 0);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void autoboot_command_fail_handle(void)
|
|
{
|
|
#ifdef CONFIG_AVB_VBMETA_PUBLIC_KEY_VALIDATE
|
|
#ifdef CONFIG_ANDROID_AB
|
|
run_command("fastboot usb 0;", 0); /* use fastboot to ative slot */
|
|
#else
|
|
run_command("rockusb 0 ${devtype} ${devnum}", 0);
|
|
run_command("fastboot usb 0;", 0);
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_FIT_ROLLBACK_PROTECT
|
|
|
|
#define FIT_ROLLBACK_INDEX_LOCATION 0x66697472 /* "fitr" */
|
|
|
|
int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
|
|
{
|
|
#ifdef CONFIG_OPTEE_CLIENT
|
|
u64 index;
|
|
int ret;
|
|
|
|
ret = trusty_read_rollback_index(FIT_ROLLBACK_INDEX_LOCATION, &index);
|
|
if (ret) {
|
|
if (ret != TEE_ERROR_ITEM_NOT_FOUND)
|
|
return ret;
|
|
|
|
index = 0;
|
|
printf("Initial otp index as %d\n", fit_index);
|
|
}
|
|
|
|
*otp_index = (uint32_t)index;
|
|
#else
|
|
*otp_index = 0;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fit_write_trusty_rollback_index(u32 trusty_index)
|
|
{
|
|
if (!trusty_index)
|
|
return 0;
|
|
|
|
return trusty_write_rollback_index(FIT_ROLLBACK_INDEX_LOCATION,
|
|
(u64)trusty_index);
|
|
}
|
|
#endif
|
|
|
|
void board_quiesce_devices(void *images)
|
|
{
|
|
hotkey_run(HK_CMDLINE);
|
|
hotkey_run(HK_CLI_OS_GO);
|
|
|
|
#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
|
|
/* Destroy atags makes next warm boot safer */
|
|
atags_destroy();
|
|
#endif
|
|
|
|
#ifdef CONFIG_ROCKCHIP_REBOOT_TEST
|
|
do_reset(NULL, 0, 0, NULL);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FIT_ROLLBACK_PROTECT
|
|
int ret;
|
|
|
|
ret = fit_write_trusty_rollback_index(gd->rollback_index);
|
|
if (ret) {
|
|
panic("Failed to write fit rollback index %d, ret=%d",
|
|
gd->rollback_index, ret);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ROCKCHIP_HW_DECOMPRESS
|
|
misc_decompress_cleanup();
|
|
#endif
|
|
}
|