a668abfcdb
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Change-Id: I87e05aa2d038997a6681d664605c0de9ca6d51bd Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit 10509987285515b0a969c39ef7374fea3545851b) |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| altera_spi.c | ||
| ath79_spi.c | ||
| atmel_spi.c | ||
| atmel_spi.h | ||
| cadence_qspi.c | ||
| cadence_qspi.h | ||
| cadence_qspi_apb.c | ||
| cf_spi.c | ||
| davinci_spi.c | ||
| designware_spi.c | ||
| exynos_spi.c | ||
| fsl_dspi.c | ||
| fsl_espi.c | ||
| fsl_qspi.c | ||
| fsl_qspi.h | ||
| ich.c | ||
| ich.h | ||
| kirkwood_spi.c | ||
| lpc32xx_ssp.c | ||
| mpc8xx_spi.c | ||
| mpc8xxx_spi.c | ||
| mvebu_a3700_spi.c | ||
| mxc_spi.c | ||
| mxs_spi.c | ||
| nds_ae3xx_spi.c | ||
| omap3_spi.c | ||
| pic32_spi.c | ||
| rk_spi.c | ||
| rk_spi.h | ||
| rockchip_sfc.c | ||
| sandbox_spi.c | ||
| sh_qspi.c | ||
| sh_spi.c | ||
| sh_spi.h | ||
| soft_spi.c | ||
| soft_spi_legacy.c | ||
| spi-emul-uclass.c | ||
| spi-mem-nodm.c | ||
| spi-mem.c | ||
| spi-uclass.c | ||
| spi.c | ||
| stm32_qspi.c | ||
| tegra20_sflash.c | ||
| tegra20_slink.c | ||
| tegra114_spi.c | ||
| tegra210_qspi.c | ||
| tegra_spi.h | ||
| ti_qspi.c | ||
| xilinx_spi.c | ||
| zynq_qspi.c | ||
| zynq_spi.c | ||