Joseph Chen 2ca0cbb64a dm: sysreset: disable psci sysreset for SPL and TPL ... SPL is the stage early than atf/op-tee that psci sysreset is not supported. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I46b988b3776638265bf8f374a10f9027d1ebc90f		2020-04-22 18:07:21 +08:00
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Kconfig	sysreset: Kconfig: default enable SYSRESET_PSCI for rockchip platforms	2018-04-18 10:09:59 +08:00
Makefile	dm: sysreset: disable psci sysreset for SPL and TPL	2020-04-22 18:07:21 +08:00
sysreset-syscon-reboot.c	dm: sysreset: support mode args for reboot/reset command	2019-11-12 19:34:04 +08:00
sysreset-uclass.c	dm: sysreset: disable psci sysreset for SPL and TPL	2020-04-22 18:07:21 +08:00
sysreset_ast.c	aspeed: Refactor AST2500 RAM Driver and Sysreset Driver	2017-05-08 11:57:32 -04:00
sysreset_psci.c	dm: Fix up inclusion of common.h	2017-06-01 07:03:03 -06:00
sysreset_rockchip.c	sysreset: rockchip: use dev_read_addr_ptr get cru base	2018-03-06 15:29:45 +08:00
sysreset_sandbox.c	dm: sandbox: sysreset: Convert driver to livetree	2017-06-01 07:03:17 -06:00
sysreset_snapdragon.c	dm: Rename dev_addr..() functions	2017-06-01 07:03:01 -06:00
sysreset_sti.c	treewide: replace with error() with pr_err()	2018-01-17 15:27:28 +08:00
sysreset_syscon.c	treewide: replace with error() with pr_err()	2018-01-17 15:27:28 +08:00
sysreset_watchdog.c	treewide: replace with error() with pr_err()	2018-01-17 15:27:28 +08:00
sysreset_xtfpga.c	…