rv1126-uboot/arch/powerpc/cpu/mpc85xx
Andy Fleming e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
..
Makefile spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL 2012-11-26 15:41:24 -06:00
b4860_ids.c powerpc/mpc85xx: Add B4860 and variant SoCs 2012-10-22 14:31:24 -05:00
b4860_serdes.c powerpc/mpc85xx: Add B4860 and variant SoCs 2012-10-22 14:31:24 -05:00
cache.c
cmd_errata.c powerpc/mpc85xx: Add workaround for DDR erratum A004934 2012-10-22 14:31:29 -05:00
commproc.c
config.mk
cpu.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00
cpu_init.c powerpc/mpc85xx: add comma before "already enabled" 2012-11-26 15:41:20 -06:00
cpu_init_early.c
ddr-gen1.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00
ddr-gen2.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00
ddr-gen3.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00
ether_fcc.c
fdt.c poweprc/85xx: add QMan frequency info and fdt fixup. 2012-10-22 15:52:46 -05:00
fixed_ivor.S
fsl_corenet2_serdes.c
fsl_corenet2_serdes.h
fsl_corenet_serdes.c powerpc/mpc85xx: sparse fixes 2012-11-04 11:00:36 -07:00
fsl_corenet_serdes.h
interrupts.c
liodn.c
mp.c powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 2012-10-22 14:31:32 -05:00
mp.h powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 2012-10-22 14:31:32 -05:00
mpc8536_serdes.c
mpc8544_serdes.c
mpc8548_serdes.c
mpc8568_serdes.c
mpc8569_serdes.c
mpc8572_serdes.c
p1010_serdes.c
p1021_serdes.c
p1022_serdes.c
p1023_serdes.c
p2020_serdes.c
p2041_ids.c
p2041_serdes.c
p3041_ids.c
p3041_serdes.c
p4080_ids.c
p4080_serdes.c
p5020_ids.c
p5020_serdes.c
p5040_ids.c
p5040_serdes.c
pci.c
portals.c mpc85xx/portals: Add qman and bman ip_cfg field into portal info 2012-10-22 15:52:46 -05:00
qe_io.c
release.S powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 2012-10-22 14:31:32 -05:00
resetvec.S
serial_scc.c
speed.c poweprc/85xx: add QMan frequency info and fdt fixup. 2012-10-22 15:52:46 -05:00
spl_minimal.c spl/85xx: new SPL support 2012-11-26 15:41:25 -06:00
start.S spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL 2012-11-26 15:41:24 -06:00
t4240_ids.c powerpc/mpc85xx: Add T4240 SoC 2012-10-22 14:31:23 -05:00
t4240_serdes.c powerpc/mpc85xx: Add T4240 SoC 2012-10-22 14:31:23 -05:00
tlb.c spl/85xx: new SPL support 2012-11-26 15:41:25 -06:00
traps.c arch/powerpc/lib/board.c, *traps.c: sparse fixes 2012-11-04 11:00:35 -07:00
u-boot-nand.lds
u-boot-nand_spl.lds
u-boot-spl.lds spl/85xx: new SPL support 2012-11-26 15:41:25 -06:00
u-boot.lds